Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI Design Group 3: Hagen Fischer, Jacob Maxa Results of Phase 2: Optimization Institute MD, University of Rostock

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 2 Challenge Improve the foreign VHDL design with regard to the metric –Optimize the filter structure –Optimize the multiplier –Optimize the adder –Step 1: Changing the direct form from I to II –Critical path only one adder instead of 8 –All multiplications in parallel ++ + Direct form II +++ Direct form I

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 3 Filter – Shrinking and pipelining FormSpeedAreaMetricImprovement* DF I (8 bit input)97,513 MHz528 LUTFF Pairs184,68 kHz/area16,893 DF 2 (8 bit input)137,774 MHz350 LUTFF Pairs393,64 kHz/area36,007 DF 2 + Pipeline (3)345,185 MHz597 LUTFF Pairs578,20 kHz/area52,889 * Metric from Phase 1: 10, kHz/area

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 4 Filter – Multiplier Multiplier Sign ext. Sign XOR b 3 b 2 b 1 b 0 Move the sign extension to the filter input Create specialized multipliers for each coefficient No coefficient input needed Based on shift operation and addition with ripple carry adders Wallace structure for internal adders Only 10 variable bit size adders for all multipliers Multiplier Sign ext. XOR

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 5 Filter – Adder Tried various adders Carry Skip Adder Carry Save Adder Ripple Carry Adder also pipelined Carry Lookahead Adder Special Structures Brent Kung Adder Kogge Stone Adder Ling Adder Result for heuristic analysis for the best metric Ripple Carry Adder for adders in multiplier component and in filter structure +

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 6 Filter – Term sharing SATSXT x_in_r y_out Possible due coefficient optimization 0xF9, 0x02, 0x1E, 0x42, 0x53 (left to right) Save 4 multiplier units and pipeline register

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 7 Results Mandatory values for FGPA Phase 2Phase 1 UnitSynthesisBackannotationSynthesis Frequency fMHz364,034355,87250,256 Area A# LUT-FF pair # Pipeline Stages 1331 Metric MHz/# LUT-FF pair 2,42693,35730,01093 Improvement from phase 1: Synthesis: 222,04 Possible further improvements: Critical path in adders Combine partial products in the multiplayer stage within all multipliers

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock End Thanks for your attention! Questions? Slide 8