1/8/ L7 Project Step 3Copyright Joanne DeGroat, ECE, OSU1 Project Step 3 Structural Modeling and the Generate Statement

1/8/ L7 Project Step 3 Copyright Joanne DeGroat, ECE, OSU2 Project Step 3  You will implement an 8 bit ALU using the slice you constructed in Step 2 using 3 methodologies.  The first is just straight component instantiations.  The next uses component instantiations for the msb and lsb slice and then a generate for the 6 middle slices  The final uses nested generate statements.  This is adding one more level of structural hierarchy to the model.

1/8/ L7 Project Step 3 Copyright Joanne DeGroat, ECE, OSU3 Only one entity!!!!!!!!!  ENTITY my_8_bit_unit IS  PORT ( 8 bits for input of A,  8 bits for input of B,  8 bits for output of result,  the function control – P,K,R  Carry in and out);  END ENTITY;  You will use bit_vectors for the A,B, and Result

1/8/ L7 Project Step 3 Copyright Joanne DeGroat, ECE, OSU4 That entity is used for 3 architectures  First Architecture 8 component instantiations Outputs are Za, Coa  Second Architecture Component instantiations for msb and lsb Generate for rest – the inner slices 1 to 6 Outputs are Zb, Cob  Third Architecture Nested Generate statement Outputs are Zc, Coc

1/8/ L7 Project Step 3 Copyright Joanne DeGroat, ECE, OSU5 In the testbench  Component Declaration (REF the ENTITY)  Need to configure the instantiation labels to the 3 architectures FOR lbl1:unit USE ENTITY WORK.slice(compinst); FOR lbl2:unit USE ENTITY WORK.slice(generate1); FOR lbl3:unit USE ENTITY WORK.slice(generate3);  Label and instantiations lbl1: slice PORT MAP(******);  Note that test inputs are the same to all 3 architectures but there are 3 separate outputs Be sure to wire up to the correct one for these connections  Use the format files (.do s) Sum_a and Coa is checked by the error signal.