MBG 1 CIS501, Fall 99 Lecture 18: Input/Output (I/O): Buses and Peripherals Michael B. Greenwald Computer Architecture CIS 501 Fall 1999

MBG 2 CIS501, Fall 99 I/O Systems Processor Cache Memory - I/O Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network interrupts Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap)

MBG 3 CIS501, Fall 99 Motivation: Who Cares About I/O? CPU Performance: 50% to 100% per year Multiprocessor supercomputers 150% per year I/O system performance limited by mechanical delays < 5% per year (IO per sec or MB per sec) Amdahl's Law: system speed-up limited by the slowest part! 10% IO & 10x CPU => 5x Performance (lose 50%) 10% IO & 100x CPU => 10x Performance (lose 90%) I/O bottleneck: Diminishing fraction of time in CPU Diminishing value of faster CPUs

MBG 4 CIS501, Fall 99 Bus-Based Interconnect Bus: a shared communication path between subsystems –Low cost: a single set of wires is shared multiple ways –Versatility: Easy to add new devices & peripherals may even be ported between computers using common bus (standardization) Disadvantage –A communication bottleneck, possibly limiting the maximum I/O throughput, (eventually limiting system performance) Bus speed is limited by physical factors –the bus length –the number of devices (and, hence, bus loading). –these physical limits prevent arbitrary bus speedup.

MBG 5 CIS501, Fall 99 Bus-Based Interconnect Two generic types of busses: –I/O busses: lengthy, many types of devices connected, wide range in the data bandwidth, and follow a bus standard. Sometimes called a channel. –CPU–memory buses: high speed, matched to the memory system to maximize memory–CPU bandwidth, single device (actually, also a small number of devices, but known in advance!). Sometimes called a backplane. –To lower costs, low cost (older) systems combine the memory and I/O buses in one shared bus »Often, system starts with one shared bus, but memory and CPU increase in speed faster than devices do, so old memory bus becomes new I/O bus. Bus transaction –Sending address & receiving or sending data

MBG 6 CIS501, Fall 99 Bus Options (See Figure 6.9, page 497)

MBG 7 CIS501, Fall 99 Example: VME bus 3 96-pin connectors 128 defined as standard, rest available for extension –32 address –32 data –64 command & power/ground lines IEEE 1014 is standard Up to.5 meters Up to 21 devices Multiple Masters

MBG 8 CIS501, Fall 99 Bus Options (See Figure 6.9, page 497)

MBG 9 CIS501, Fall 99 Bus Options (See Figure 6.9, page 497) Need to understand bus transaction

MBG 10 CIS501, Fall 99 Bus Protocols ° ° ° MasterSlave Control Lines Address Lines Data Lines Bus Master : has ability to control the bus, initiates transaction Bus Slave : module activated by the transaction Bus Communication Protocol : specification of sequence of events and timing requirements in transferring information. Asynchronous Bus Transfers: control lines (req., ack.) serve to orchestrate sequencing Synchronous Bus Transfers: sequence relative to common clock

MBG 11 CIS501, Fall 99 Synchronous Bus Protocols Address Data Read Wait Clock Address Data Wait Pipelined/Split transaction Bus Protocol (a.k.a. packet-switched bus) addr 1 data 0 addr 2 wait 1 data 1 addr 3 OK 1 data 2 begin read Read complete Master Slave

MBG 12 CIS501, Fall 99 Asynchronous Handshake Write Transaction Address Data Read Req. Ack. Master Asserts Address Master Asserts Data Next Address t0 t1 t2 t3 t4 t5 t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating data received t3: Master releases req t4: Slave releases ack 4 Cycle Handshake

MBG 13 CIS501, Fall 99 Asynchronous Handshake Read Transaction Address Data Read Req Ack Master Asserts AddressNext Address t0 t1 t2 t3 t4 t5 Time Multiplexed Bus: address and data share lines t0 : Master has obtained control and asserts address, direction, data Waits a specified amount of time for slaves to decode target\ t1: Master asserts request line t2: Slave asserts ack, indicating ready to transmit data t3: Master releases req, data received t4: Slave releases ack 4 Cycle Handshake

MBG 14 CIS501, Fall 99 Time Multiplexed Bus Definition: address and data share lines, fewer lines –Cheaper –Slower –More complex protocols Need some way of distinguishing between addr and data, start and end of xaction. –In-band: delimiters, tokens, header/trailer –Out-of-band: control lines.

MBG 15 CIS501, Fall 99 Bus Arbitration Parallel (Centralized) Arbitration Serial Arbitration: (logical) daisy chaining,fixed priority Polling BR BG M M M M BGi BGo BR M BGi BGo BR M BGi BGo BR BG BR A.U. BR A C M M M BR A A.U. Bus Request Bus Grant

MBG 16 CIS501, Fall 99 Processor Interface Issues How does bus interface with/to processor? Interconnections/Buses – Shared vs. separate Memory/IO buses – Attach to memory, cache, or proc.(separate only) Processor communication interface –I/O interface vs. Memory mapped I/O I/O Control Structure –Polling –Interrupts –DMA –I/O Controllers –I/O Processors

MBG 17 CIS501, Fall 99 Shared Bus Processor Cache Memory - I/O Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network interrupts Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap)

MBG 18 CIS501, Fall 99 Separate Buses Processor Cache Memory Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network interrupts Time(workload) = Time(CPU) + Time(I/O) - Time(Overlap) (More overlap between I/O and Memory buses). I/O Bus Bus Adaptor

MBG 19 CIS501, Fall 99 Processor Interface Issues How does bus interface with/to processor? Interconnections/Buses – Shared vs. separate Memory/IO buses – Attach to memory, cache, or proc.(separate only) Processor communication interface –I/O interface vs. Memory mapped I/O I/O Control Structure –Polling –Interrupts –DMA –I/O Controllers –I/O Processors

MBG 20 CIS501, Fall 99 Connection point: memory Processor Cache Memory Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network interrupts Stale data, consistency traffic. I/O Bus Bus Adaptor

MBG 21 CIS501, Fall 99 Connection point: cache Processor Cache Memory Bus Main Memory I/O Controller Disk I/O Controller I/O Controller Graphics Network interrupts No Stale data, but lost performance because of cache pollution and arbitration between I/O and CPU on cache access (increase hit time/cycle time?) I/O Bus Bus Adaptor

MBG 22 CIS501, Fall 99 Processor Interface Issues How does bus interface with/to processor? Interconnections/Buses – Shared vs. separate Memory/IO buses – Attach to memory, cache, or proc.(separate only) Processor communication interface –I/O interface vs. Memory mapped I/O I/O Control Structure –Polling –Interrupts –DMA –I/O Controllers –I/O Processors

MBG 23 CIS501, Fall 99 How does processor access I/O devices? Need to read and write control and status registers. Need to transfer data to/from I/O device

MBG 24 CIS501, Fall 99 I/O Interface Independent I/O Bus CPU Interface Peripheral Memory memory bus Seperate I/O instructions (in,out) CPU Interface Peripheral Memory Lines distinguish between I/O and memory transfers common memory & I/O bus VME bus Multibus-II Nubus 40 Mbytes/sec optimistically 10 MIP processor completely saturates the bus!

MBG 25 CIS501, Fall 99 Memory Mapped I/O Single Memory & I/O Bus No Separate I/O Instructions CPU Interface Peripheral Memory ROM RAM I/O $ CPU L2 $ Memory Bus MemoryBus Adaptor I/O bus Bus Adaptor snoops memory bus transactions and converts I/O space addresses to I/O operations on I/O bus. (converts I/O ops to memory reads and writes, too).

MBG 26 CIS501, Fall 99 I/O Architecture Hardware covers interconnection point and number of buses. Software architecture: how I/O is managed by processor(s).