Hardware proposal for the L2  trigger system detailed description of the architecture mechanical considerations components consideration electro-magnetic compatibility work & manpower Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot April the 26 th, 2001

CPU board Processor : Pentium III 850 MHz Dimensions : 6U Make : VMIC Type : VMIVME-7740 CPU board Processor : Pentium III 850 MHz Dimensions : 6U Make : VMIC Type : VMIVME-7740 Trigger Crate Trigger adaptation board Function : interface between the trigger crate and the processor board Trigger adaptation board Function : interface between the trigger crate and the processor board PCI bus 33 MHz, 32 bits VME bus Magic bus 128 data bits 32 add bits 20 MHz ECL signals L2 trigger mosaic of boards Functionnal diagram

6U board 366 mm 160 mm 400 mm 233 mm 9U board Dimensions

Hard drive The proportions of the boards are respected 6U board 9U board mezzanine board Architecture of the system

Hard drive The proportions of the boards are respected 6U board 9U board mezzanine board Additionnal rigidity bars rigidity bar

9U board VME The proportions of the boards are respected XCV405E BGA 676 Mechanics placement

Hard drive The proportions of the boards are respected 6U board 9U board mezzanine board Electronics functionalities rigidity bar Local bus Magic bus PCI VME EIDE drivers : electrical isolation VME electrical conversion to ECL Display PCI / local bus interface Add-on / Magic bus interface & PCI / Magic bus arbitration FPGA 20 MHz 33 MHz drivers

FPGA requirements numerous signals : 380 signal pins necessary moderate logics : cells large memory : 73 kB high rate : mostly 33MHz, a few cells at 66 MHz low power consumption : no radiator compact package : less sensitive to the board torsion less room on board unique FPGA : flexibility

FPGA characteristics Xilinx Virtex-E 1.8V Extended memory : XCV405E wide logics capacity : cells, 70 kB RAM kB configurable RAM high rate : 130 MHz internal performance low voltage : 1.8 V core, 3.3V I/O, <300 mW compact package : Fineline BGA 676, 404 signal pins 1mm pitch, 27mm side, 2.25mm height clocks : DLL x2 x4 to generate 66 and 132 from 33 MHz not fully 5V compatible : connects to 3.3V components

Magic bus Control signals from J1 and J2 connectors ECL drivers data and control signals Display FPGA details 203 Xilinx XCV405E Fineline BGA local bus test connector 32 5 Switches 4 Total : 382 signals out of 404 available 27 mm height : 2.25 mm the geometry of the input/output pins is not respected

PLX9054 TTL drivers FIFO Xilinx XCV405E MB Local bus the diagram is greatly simplified by the integration of the FIFOs inside the FPGA FPGA’s data busses diagram 32 PCI

PCI interface characteristics PLX 9054, 32 bits, 33 MHz, PCI norm v2.2 PCI master and slave functionnalities supports DMA, and programmed I/O access types in both directions 5V and 3.3V compatible package : PQFP mm pitch, 26mm side, 2.7mm height BIOS is loaded from an EEPROM

Hard drive The proportions of the boards are respected 6U board 9U board mezzanine board placement of the components rigidity bar local bus Magic bus PCI VME EIDE Xilinx Virtex-E Extended Memory XCV405E Fineline BGA 676 PLX 9054 PQFP 176 TTL driver TTL drivers VME EPROM ECL drivers Display EPROM XCV405E BGA 676

The proportions of the boards are respected 6U board9U board Geometry of the boards (profile view) Hard drive 9U board PCI interface 6U components sidemezzanine components side 9U components side (a few thin (height : 1.20 mm) TTL drivers will be on the other side) TTL drivers ~12mm

PCI PLX9054 PQFP 176 EPROM local bus Flex cables : flexibility on the position of the PMC connectors the mezzanine board is relatively simple local bus vertical position adjustable of a few centimeters horizontal position adjustable of a few millimeters

Electro-magnetic compatibility Environment : Very noisy 850 MHz processor, 100 MHz system bus,... Receptivity : moderate on the SBC: only digital moderate on the 9U and mezzanine boards but ground loops in the system to avoid EMC considerations : a few ground loops exist, but are very small the 2-slot architecture is to avoid

The proportions of the boards are respected 6U board 9U board mezzanine board Grounding of the boards back plane

PCBs and hardware to design a 9U board a mezzanine board the 9U front panel the rigidity bars no modification on the 6U board

The proportions of the boards are respected 9U board from the factory

The proportions of the boards are respected assembly of the backplane connectors

The proportions of the boards are respected assembly of the rigidity bars

The proportions of the boards are respected board fully assembled TTL drivers EPROM ECL drivers XCV405E BGA 676 TTL driver EIDE

Hard drive The proportions of the boards are respected 6U board 9U board mezzanine board Whole L2  system rigidity bar local bus Magic bus PCI VME EIDE Xilinx Virtex-E Extended Memory XCV405E Fineline BGA 676 PLX 9054 PQFP 176 TTL driver TTL drivers VME EPROM ECL drivers Display EPROM XCV405E BGA 676 VME

Manpower at Orsay schematics, firmware : Bernard Lavigne, Philippe Cros (+ a technician if necessary) tests : Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot PCB design : board design group front panel, rigidity bars, mechanics questions : mechanics group production, assembly : private companies

Costs (US $) prototype (3)production (30) PCB Components Assembly Total Whole budget : $ The front panel and mechanics components are taken in account in the components budget The costs don’t count the CPU board, neither the engineering cost which is around $20000 PCB Components10050 Assembly50500 assembled at Orsay nota : 9U mezzanine

Conclusion : The hardware solution we propose : cheap realistic schedule and architecture manpower and experience technically reliable flexible, simple