1 IKI20210 Pengantar Organisasi Komputer Kuliah No. 20: DMA & Standard I/O Bus 27 November 2002 Bobby Nazief Johny Moningka bahan kuliah: Sumber: 1. Hamacher. Computer Organization, ed Materi kuliah CS152, th. 1997, UCB. 3. Materi kuliah CS61C, th. 2000, UCB.

2 Review: I/O – OS – User’s Program I/O Device User’s Program I/O Services Device Driver OS getchar(); System.in.readLine(); putchar(); System.out.println(); Device Driver

3 Improving Data Transfer Performance °Thus far: OS give commands to I/O, I/O device notify OS when the I/O device completed operation or an error °What about data transfer to I/O device? Processor busy doing loads/stores between memory and I/O Data Register: Wait: sbisDiskControl,1; is Disk ready? rjmpWait; no inr0,DiskData; get byte stX+,r0; store it decr16; done? bneWait; not yet °Ideal: specify the block of memory to be transferred, be notified on completion? Direct Memory Access (DMA) : a simple computer transfers a block of data to/from memory and I/O without involving the processor, interrupting upon done

4 Delegating I/O Responsibility from the CPU: DMA °Direct Memory Access (DMA): External to the CPU Act as a maser on the bus Transfer blocks of data to or from memory without CPU intervention CPU IOC device Memory DMAC CPU sends a starting address, direction, and length count to DMAC. Then issues "start". DMAC provides handshake signals for Peripheral Controller, and Memory Addresses and handshake signals for Memory. Issue: Who controls the BUS? (CPU or DMAC may do so) How?

5 Bus Arbitration

6 Arbitration: Obtaining Access to the Bus °One of the most important issues in bus design: How is the bus reserved by a devices that wishes to use it? °Chaos is avoided by a master-slave arrangement: Only the bus master can control access to the bus: It initiates and controls all bus requests A slave responds to read and write requests °The simplest system: Processor is the only bus master All bus requests must be controlled by the processor Major drawback: the processor is involved in every transaction Bus Master Bus Slave Control: Master initiates requests Data can go either way

7 Multiple Potential Bus Masters: the Need for Arbitration °Bus arbitration scheme: A bus master wanting to use the bus asserts the bus request A bus master cannot use the bus until its request is granted A bus master must signal to the arbiter after finish using the bus °Bus arbitration schemes usually try to balance two factors: Bus priority: the highest priority device should be serviced first Fairness: Even the lowest priority device should never be completely locked out from the bus °Bus arbitration schemes can be divided into four broad classes: Daisy chain arbitration: single device with all request lines. Centralized, parallel arbitration: see next-next slide Distributed arbitration by self-selection: each device wanting the bus places a code indicating its identity on the bus. Distributed arbitration by collision detection: Ethernet uses this.

8 The Daisy Chain Bus Arbitrations Scheme °Advantage: simple °Disadvantages: Cannot assure fairness: A low-priority device may be locked out indefinitely The use of the daisy chain grant signal also limits the bus speed Bus Arbiter Device 1 Highest Priority Device N Lowest Priority Device 2 Grant Release Request wired-OR

9 Centralized Parallel Arbitration °Used in essentially all processor-memory busses and in high-speed I/O busses Bus Arbiter Device 1 Device N Device 2 Grant Req

10 More on BUS

11 Types of Buses °Processor-Memory Bus (design specific) Short and high speed Only need to match the memory system -Maximize memory-to-processor bandwidth Connects directly to the processor Optimized for cache block transfers °I/O Bus (industry standard) Usually is lengthy and slower Need to match a wide range of I/O devices Connects to the processor-memory bus or backplane bus °Backplane Bus (standard or proprietary) Backplane: an interconnection structure within the chassis Allow processors, memory, and I/O devices to coexist Cost advantage: one bus for all components

12 A Computer System with One Bus: Backplane Bus °A single bus (the backplane bus) is used for: Processor to memory communication Communication between I/O devices and memory °Advantages: Simple and low cost °Disadvantages: slow and the bus can become a major bottleneck °Example: IBM PC - AT ProcessorMemory I/O Devices Backplane Bus

13 A Two-Bus System °I/O buses tap into the processor-memory bus via bus adaptors: Processor-memory bus: mainly for processor-memory traffic I/O buses: provide expansion slots for I/O devices °Apple Macintosh-II NuBus: Processor, memory, and a few selected I/O devices SCCI Bus: the rest of the I/O devices ProcessorMemory I/O Bus Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus I/O Bus

14 A Three-Bus System °A small number of backplane buses tap into the processor-memory bus Processor-memory bus is used for processor memory traffic I/O buses are connected to the backplane bus °Advantage: loading on the processor bus is greatly reduced ProcessorMemory Processor Memory Bus Bus Adaptor Bus Adaptor Bus Adaptor I/O Bus ( e.g., SCSI ) Backplane Bus ( e.g., PCI ) I/O Bus

15 What defines a bus? Bunch of Wires Physical / Mechanical Characterisics – the connectors Electrical Specification Timing and Signaling Specification Transaction Protocol

16 Synchronous and Asynchronous Bus °Synchronous Bus: Includes a clock in the control lines A fixed protocol for communication that is relative to the clock Advantage: involves very little logic and can run very fast Disadvantages: -Every device on the bus must run at the same clock rate -To avoid clock skew, they cannot be long if they are fast °Asynchronous Bus: It is not clocked It can accommodate a wide range of devices It can be lengthened without worrying about clock skew It requires a handshaking protocol

17 Simplest bus paradigm °All agents operate syncronously °All can source / sink data at same rate °=> simple protocol just manage the source and target

18 Simple Synchronous Protocol °Even memory busses are more complex than this memory (slave) may take time to respond it need to control data rate BReq BG Cmd+Addr R/W Address Data1Data2 Data

19 Typical Synchronous Protocol °Slave indicates when it is prepared for data xfer °Actual transfer goes at bus rate BReq BG Cmd+Addr R/W Address Data1Data2 Data Data1 Wait

20 Asynchronous Handshake Address Data Write Req Ack Master Asserts Address Master Asserts Data Next Address Write Transaction t0 t1 t2 t3 t4 t5 °t0 : Master has obtained control and asserts address, direction, data ° Waits a specified amount of time for slaves to decode target °t1: Master asserts request line °t2: Slave asserts ack, indicating data received °t3: Master releases req °t4: Slave releases ack

21 Read Transaction Address Data Read Req Ack Master Asserts AddressNext Address t0 t1 t2 t3 t4 t5 °t0 : Master has obtained control and asserts address, direction, data ° Waits a specified amount of time for slaves to decode target\ °t1: Master asserts request line °t2: Slave asserts ack, indicating ready to transmit data °t3: Master releases req, data received °t4: Slave releases ack

22 I/O BUS

23 The I/O Bus Problem °Designed to support wide variety of devices full set not know at design time °Allow data rate match between arbitrary speed deviced fast processor – slow I/O slow processor – fast I/O

24 PCI: Peripheral Component Interconnect

25 PCI Read/Write Transactions °All signals sampled on rising edge °Centralized Parallel Arbitration °All transfers are (unlimited) bursts °Address phase starts by asserting FRAME# °Next cycle “initiator” asserts cmd and address °Data transfers happen on when IRDY# asserted by master when ready to transfer data TRDY# asserted by target when ready to transfer data transfer when both asserted on rising edge °FRAME# deasserted when master intends to complete only one more data transfer

26 PCI Read Transaction – Turn-around cycle on any signal driven by more than one agent

27 PCI Write Transaction

28 PCI Optimizations °Push bus efficiency toward 100% under common simple usage like RISC °Bus Parking retain bus grant for previous master until another makes request granted master can start next transfer without arbitration °Arbitrary Burst length intiator and target can exert flow control with xRDY target can disconnect request with STOP (abort or retry) master can disconnect by deasserting FRAME arbiter can disconnect by deasserting GNT °Delayed (pended, split-phase) transactions free the bus after request to slow device

Backplane/IO Bus Survey BusSBusTurboChannelMicroChannelPCI OriginatorSunDECIBMIntel Clock Rate (MHz) async33 AddressingVirtualPhysicalPhysicalPhysical Data Sizes (bits)8,16,328,16,24,328,16,24,32,648,16,24,32,64 MasterMultiSingleMultiMulti ArbitrationCentralCentralCentralCentral 32 bit read (MB/s) Peak (MB/s) (222) Max Power (W)

30 SCSI: Small Computer System Interface °Asynchronous Bus °Distributed Arbitration by Self-selection °Data transfers happen on when: C/D is deasserted by initiator I/O determines transfer direction between initiator & target REQ is asserted by target to request transfer cycle ACK is asserted by initiator when it has completed a transfer

31 SCSI Signals Description Signal Description BSY indicates that the bus is being used SEL used by an initiator to select a target, or by a target to reselect an initiator. C/D indicates control or data information is on the data bus I/0 control the direction of data movement on the data bus MSG driven by a target during the Message phase REQ driven by a target to request a REQ/ACK handshake ACK driven by an initiator to acknowledge a REQ/ACK ATN driven by an initiator to indicate the attention condition (indicator has a message for the target). RST hard reset condition DB 8 data-bit signals, plus a parity-bit signal that form a Data Bus DB(7) is the most significant bit and has the highest prioty Bit number, significance, and priority decrease downward

32 SCSI Arbitration

33 SCSI Read/Write Transactions

34 SCSI Roadmap

35 SCSI Bus Characteristics Type Bus Width (bits) Bus Speed (MB's/sec) Max. Devices Bus Length (Meters) SCSI Fast SCSI81083 Ultra SCSI Ultra2 SCSI LVD Fast Wide SCSI Ultra Wide SCSI Ultra2 Wide SCSI Ultra3 SCSI Ultra320 SCSI

36 Summary of Bus Options °OptionHigh performanceLow cost °Bus widthSeparate addressMultiplex address & data lines& data lines °Data widthWider is fasterNarrower is cheaper (e.g., 32 bits)(e.g., 8 bits) °Transfer sizeMultiple words hasSingle-word transfer less bus overheadis simpler °Bus mastersMultipleSingle master (requires arbitration)(no arbitration) °ClockingSynchronousAsynchronous °ProtocolpipelinedSerial