Progress Report: P1149.8.1 Kenneth P. Parker Agilent Technologies Loveland, CO Board Test Workshop, 2010.

Slides:



Advertisements
Similar presentations
Introduction to DFT Alexander Gnusin.
Advertisements

TA Jet Apply the theory of electrostatic strength measurement to detect the solder joints open / contacted BGA pins up to 100%.
Compensation for Measurement Errors Due to Mechanical Misalignments in PCB Testing Anura P. Jayasumana, Yashwant K. Malaiya, Xin He, Colorado State University.
© 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 1 Ted Eaton coerced by the late Bill Eklow 9/15/ Cross-over issue.
Lecture 28 IEEE JTAG Boundary Scan Standard
Latches Module M10.1 Section 7.1. Sequential Logic Combinational Logic –Output depends only on current input Sequential Logic –Output depends not only.
BSDL Extensions for dot6 Michael Sberro JTAG course 2005 Michael Sberro JTAG course 2005.
Improved Boundary Scan Design (Based on a paper by Lee Whetsel, Texas Instruments Inc.)
Real-Time Systems Design JTAG – testing and programming.
CR1000s are only one part of a data acquisition system. To get good data, suitable sensors and a reliable data retrieval method are required. A failure.
TAP (Test Access Port) JTAG course June 2006 Avraham Pinto.
Guidelines for Chip DFT Based on Boundary Scan Reference to an article by Ben Bannetts By Regev Susid.
Timers and Interrupts Shivendu Bhushan Summer Camp ‘13.
Configuration. Mirjana Stojanovic Process of loading bitstream of a design into the configuration memory. Bitstream is the transmission.
M.S.P.V.L. Polytechnic College, Pavoorchatram
CR1000s are only one part of a data acquisition system. To get good data, suitable sensors and a reliable data retrieval method are required. A failure.
Digital I/O Connecting to the Outside World
Computer… An electronic machine Monitor Mouse Printer (Inkjet) Key Board Cabinet UPS PPT
What is a Microcontroller? Computer on a Chip Microprocessor Input / Output RAM and/or ROM Signal Processing.
1 EE 587 SoC Design & Test Partha Pande School of EECS Washington State University
IEEE Std 1581 is published … Now what? 2011 Board Test Workshop Heiko Ehrenberg.
Enhancing the Capabilities of a Wireless Holter Monitor Senan Garry 4 th ECE.
Computerized Train Control System by: Shawn Lord Christian Thompson.
Baseboard Aavikkomursu 7.2. Aavikkomursu Micro- controller Extension port for programming microcontroller and sensor input Resistor RS485 interface chip.
 What Is a Computer? What Is a Computer?  Computer System Components Computer System Components  Hardware Hardware  Types of Memory Types of Memory.
Design for Test HIBU – Oct. 31st 2006 J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 J. M. Martins Ferreira FEUP / DEEC - Rua Dr.
Rabie A. Ramadan Lecture 3
Xin He, Yashwant Malaiya, Anura P. Jayasumana Kenneth P
© 2008 Cisco Systems, Inc. All rights reserved.Cisco ConfidentialPaper #15 1 Hongshin Jun, Bill Eklow 9/15/2010 BTW10, Fort Collins, CO PCC - Programmable.
Washington State University
Updates on the 863MHz SRD band and 872MHz Award Andy Gowans, SPG, Ofcom UK 12th May 2009 IEEE802 Interim Meeting Atlanta 2009.
Model Name Transition Project Learning Network Workshop 3 IYF Transition Project.
ECG Monitor Objective o Provide users an economical ECG monitoring device o Raise awareness to the importance of a healthy heart and living o Allow doctors.
ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTEMS Boundary Scan.
Page 1 LXMG , LXMG LXMG , LXMG PanelMatch™, StayLit™ Dual Lamp CCFL Inverter Modules Training.
Team 6 DOODLE DRIVE Alexander Curtis Peachanok Lertkajornkitti | Jun Pan | Edward Kidarsa |
Aga Khan University Hospital Karachi
April 20, 2001VLSI Test: Bushnell-Agrawal/Lecture 281 Lecture 28 IEEE JTAG Boundary Scan Standard n Motivation n Bed-of-nails tester n System view.
Embedded Network Interface (ENI). What is ENI? Embedded Network Interface Originally called DPO (Digital Product Option) card Printer without network.
Brandon Robinson Danut Tabacaru Victor Ho Autonomous Spacecraft Impact Monitoring Preliminary design presentation Autonomous Spacecraft Impact Monitoring.
Microcomputer Systems Final Project “Speaker and Sound Modulation”
Toshiba Infrared (IR) Test Apparatus Project Nurfazlina Kamaruddin Ahmad Nazri Fadzal Wan Othman Zamir Izam.
© J. M. Martins Ferreira - University of Porto (FEUP / DEEC)1 IEEE Standard : Boundary-Scan Testing of Advanced Digital Networks J. M. Martins Ferreira.
AIDA ASIC review Davide Braga Steve Thomas ASIC Design Group 11 February 2009.
Overview for Initialization Process April 27, 2010.
Proximity Sensors. What are proximity sensors is a sensor able to detect the presence of nearby objects without any physical contact.sensor.
Boundary-Scan driven Vectorless Testing on Active Components Steve Hird Loveland, CO.
Ambilight™ 2K6 Pieter Risseeuw January High-End TV, Pieter Risseeuw2 The converter boards: Double stuffed converter board For sets with 3 or 4 sided.
SYSTEM-LEVEL TEST TECHNIQUES INTRODUCTION In the 1970s, the in-circuit testing (ICT) method appeared. In the 1970s, the in-circuit testing (ICT) method.
Presents. C IRCUIT M ASTER 4000M Mixed Signal Circuit Analyser.
Robotics for Tomorrow
Intellectual Insulation Indicator «3i»
CLUster TIMing Electronics Part II
Connector Function Input I/O Output I/O
UNIT – Microcontroller.
Flip-flops Inputs are logically disconnected from the output in time.
ACSF-C2 2-actions system
CPE/EE 428/528 VLSI Design II – Intro to Testing (Part 3)
Standard for a Mixed-Signal Test Bus Top Level Architecture
ABB i-bus® EIB / KNX Binary Input BE/S x.x.1
Erasable Programmable Logic Devices (EPLDs)
Generic Array Logic (GAL)
Updates on the 863MHz SRD band and 872MHz Award
AT28C17 EEPROM By: Ethan Peterson.
Organizational Consulting
Accredited Standards Committee C63® - EMC
API SC-16 task group for Specification 16D
Sungho Kang Yonsei University
Aciequor Workshop spAts IIT Kharagpur.
Building a Strategic Plan
Presentation transcript:

Progress Report: P Kenneth P. Parker Agilent Technologies Loveland, CO Board Test Workshop, 2010

BTW What is P ? A standard to support Boundary-Scan based stimulus for testing technologies based on capacitive sensing (a’la “TestJet”) –Aimed principally at detecting open device pins –Quite useful for “incomplete” nets, such as those with Boundary-Scan on one side, but nothing on the other (e.g, vacant connectors). Offers a new instruction “Selective_Toggle” –Can create edges, pulses and frequencies on selected I/O pins

BTW TestJet

BTW “Boundary Jet”

BTW Single-ended Pins Outputs are given the ability to selectively toggle Inputs are equipped with an output drive capability, that can selectively toggle Both are recommended to monitor their pin state while doing EXTEST (self-monitors)

BTW Differential Pins Outputs are given the ability to selectively toggle in two modes: –Balanced (normal differential) –Unbalanced (non-differential) –Both modes needed for opens testing Inputs are equipped with an output drive capability, that can selectively toggle Both are recommended to monitor their pin state while doing EXTEST (self-monitors)

BTW Differential Pin Balancing/Unbalancing

BTW Progress to Date We are closing in on a ballot draft Work remaining: –Finalize Single-ended and Differential pins –Create BSDL extension –Update Annex on P and co-existence in a single device To Ballot by New Years ? (It could happen!) Want to vote?

BTW Thank You !