Dept. of Electrical and Computer Engineering The University of Texas at Austin E-Beam Lothography Stencil Planning and Optimization wit Overlapped Characters.

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Presentation transcript:

Dept. of Electrical and Computer Engineering The University of Texas at Austin E-Beam Lothography Stencil Planning and Optimization wit Overlapped Characters

Outline Introduction Preliminary and problem formulation One dimensional stencil design Two dimensional stencil design Experimental results Conclusion

Introduction Conventional 193nm Optical Photolithography Technology Is Facing The Great Challenge Of Printing Sub-32nm.

Introduction Near future Double/multiple patterning

Introduction Longer future (to print finer feature size below 16nm) Electronic Beam Lithography (EBL) Extreme Ultra Violet (EUV) Nanoimprint Electronic Beam Lithography (EBL) Maskless technology Low throughput

Electronic Beam Lithography (EBL) Variable Shaped Beam (VSB) The layout is usually decomposed into a set of rectangles.

Electronic Beam Lithography (EBL) Character Projection (CP) Print some complex shapes in one electronic beam shot. Improving the throughput of VSB methods. Characters, or Templates are prepared on a stencil first.

Character Projection (CP)

Preliminary and problem formulation When individual character is designed, blanking space is usually reserved around its enclosed rectangular circuit pattern.

Preliminary and problem formulation Overlapped characters The space between layout A and B is (BlankA + BlankB). We would greatly reduce the total area of character A and B by sharing an amount of min (BlankA, BlankB) space.

Preliminary and problem formulation Stencil Design Challenge For each character, the amount of required blanking space is not uniform, strongly depending on its enclosed layout patterns. The main difficulty of stencil design with overlapped characters.

Preliminary and problem formulation Problem Formulation The dimensional variable of character candidates

Problem Formulation Manufacturing time of EBL is dominantly determined by electronic beam shooting. Make use of total number of shots as the measurement of projection time. The total processing time (number of shots) of the entire circuit is computed by following equation.

Problem Formulation

One dimensional stencil design All the characters have the same height, and their layouts near top and bottom boundary edges are mostly regular rails. The required blanking spaces on the top t and bottom b are nearly identical Characters are usually be placed on the stencil in a row-based manner.

One dimensional stencil design

Greedy One Dimensional Bin Packing To construct a reasonable good starting point, we adopt a descending best-fit bin packing algorithm to push the character candidates into stencil, until there is no enough capacity.

One dimensional stencil design

Best-fit packing strategy Put the candidate into the row with most blank space left.

Single Row Reordering We can adjust the relative locations of already-placed characters in each row to shrink its occupied width and increase remaining capacity.

Single Row Reordering Total occupied width can be computed as To compute optimal character permutation for maximum amount of shared blanking width, we formulate a minimum cost Hamiltonian path problem.

Multiple Row Swapping After single row reordering, the character permutation within each row has been extensively optimized. It is still possible to increase their remaining capacities, by swapping characters from different rows.

Inter Stencil Tuning To get out of local optima, as the last step of each iteration, we would like to exchange the placed characters with those which have not been selected. Randomly pick and exchange two character candidates, where one is from the stencil and another is not. The swapping will be accepted, only if the overall projection time is reduced and the remaining capacity of any row is not shrunk.

TWO DIMENSIONAL STENCIL DESIGN The blanking spaces of templates are non-uniform along both horizontal and vertical directions. NP-complete Simulated-annealing based heuristic approach Sequence Pair Representation

Step1: Transform SP to a min-area packing solution Step2: Assuming the left-bottom coordinates of packing results and stencil are the same, the candidates, which are located completely within the outline of stencil, are considered as selected characters.

Correct Packing Algorithm[16] Determine the physical coordinates of each block Weighted longest path algorithm

Fast Packing Evaluation

Simulated Annealing Throughput-driven Swapping

Slack-based insertion Add-in a new candidate, which currently is not serving as character.

EXPERIMENTAL RESULTS

Conclusion In this paper, we have developed two algorithms for overlapping aware stencil design in electronic beam lithography.