Part A Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.

Slides:



Advertisements
Similar presentations
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
Advertisements

1 SECURE-PARTIAL RECONFIGURATION OF FPGAs MSc.Fisnik KRAJA Computer Engineering Department, Faculty Of Information Technology, Polytechnic University of.
Ultrasonic signal processing platform for nondestructive evaluation (NDE) Raymond Smith Advisors: Drs. In Soo Ahn, Yufeng Lu May 6, 2014.
© 2003 Xilinx, Inc. All Rights Reserved Debugging.
Huffman Encoder Activity Report 2 Advisor:Dr.Goudarzi Advanced topics in design hardware January 2006.
טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004 Students: Nir Sheffi.
© 2004 Xilinx, Inc. All Rights Reserved Implemented by : Alon Ben Shalom Yoni Landau Project supervised by: Mony Orbach High speed digital systems laboratory.
NETWORK ON CHIP ROUTER Students : Itzik Ben - shushan Jonathan Silber Instructor : Isaschar Walter Final presentation part B Spring 2006.
Reliable Data Storage using Reed Solomon Code Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004 Part A Final Presentation.
Network based System on Chip Performed by: Medvedev Alexey Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006.
Network based System on Chip Students: Medvedev Alexey Shimon Ofir Supervisor: Walter Isaschar (Zigmond) Winter-Spring 2006.
Asynchronous Pipelined Ring Interconnection for SoC Final Presentation One semester project, Spring 2005 Supervisor: Nitzan Miron Students: Ziv Zeev Shwaitser.
Middle presentation Dynamic System on Programmable Chip By: Nir Shahar and Amir Kleinhendler Supervisor: Ina Rivkin Spring/Winter 2006.
טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Final A Presentation Students: Nir Sheffi Evgeny Bogokovsky Instructor: Isaschar Walter Winter 2004.
Performed by : Rivka Cohen and Sharon Solomon Instructor : Walter Isaschar המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון.
DSP Algorithm on System on Chip Performed by : Einat Tevel Supervisor : Isaschar Walter Accompanying engineers : Emilia Burlak, Golan Inbar Technion -
Configurable System-on-Chip: Xilinx EDK
Workload distribution in satellites Part A Final Presentation Performed by :Grossman Vadim Maslovksy Eugene Instructor:Rivkin Inna Spring 2004.
הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Virtex II-PRO Dynamical.
The Xilinx EDK Toolset: Xilinx Platform Studio (XPS) Building a base system platform.
Students:Gilad Goldman Lior Kamran Supervisor:Mony Orbach Mid-Semester Presentation Spring 2005 Network Sniffer.
1 Performed by : Rivka Cohen and Sharon Solomon Instructor : Walter Isaschar המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון.
Reliable Data Storage using Reed Solomon Code Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004 Midterm Presentation.
Technion Digital Lab Project Xilinx ML310 board based on VirtexII-PRO programmable device Students: Tsimerman Igor Firdman Leonid Firdman Leonid.
1 Fast Communication for Multi – Core SOPC Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab.
1 Chapter 14 Embedded Processing Cores. 2 Overview RISC: Reduced Instruction Set Computer RISC-based processor: PowerPC, ARM and MIPS The embedded processor.
Reliable Data Storage using Reed Solomon Code Supervised by: Isaschar (Zigi) Walter Performed by: Ilan Rosenfeld, Moshe Karl Spring 2004 Characterization.
Performed by : Rivka Cohen and Sharon Solomon Instructor : Walter Isaschar המעבדה למערכות ספרתיות מהירות High Speed Digital Systems Laboratory הטכניון.
Implementation of DSP Algorithm on SoC. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak.
הטכניון - מכון טכנולוגי לישראל הפקולטה להנדסת חשמל Technion - Israel institute of technology department of Electrical Engineering Virtex II-PRO Dynamical.
Technion Digital Lab Project Performance evaluation of Virtex-II-Pro embedded solution of Xilinx Students: Tsimerman Igor Firdman Leonid Firdman.
Implementation of DSP Algorithm on SoC. Characterization presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompany engineer : Emilia Burlak.
This material exempt per Department of Commerce license exception TSU Debugging.
Lecture 7 Lecture 7: Hardware/Software Systems on the XUP Board ECE 412: Microcomputer Laboratory.
Using FPGAs with Embedded Processors for Complete Hardware and Software Systems Jonah Weber May 2, 2006.
General Purpose FIFO on Virtex-6 FPGA ML605 board midterm presentation
Out-of-Order OpenRISC 2 semesters project Semester A: Implementation of OpenRISC on XUPV5 board Final A Presentation By: Vova Menis-Lurie Sonia Gershkovich.
Students: Oleg Korenev Eugene Reznik Supervisor: Rolf Hilgendorf
The 6713 DSP Starter Kit (DSK) is a low-cost platform which lets customers evaluate and develop applications for the Texas Instruments C67X DSP family.
Hardware Design This material exempt per Department of Commerce license exception TSU.
© 2004 Xilinx, Inc. All Rights Reserved EDK Overview.
This material exempt per Department of Commerce license exception TSU Writing Basic Software Applications Lab 4 Introduction.
Research on Reconfigurable Computing Using Impulse C Carmen Li Shen Mentor: Dr. Russell Duren February 1, 2008.
집적회로 Spring 2007 Prof. Sang Sik AHN Signal Processing LAB.
Heng Tan Ronald Demara A Device-Controlled Dynamic Configuration Framework Supporting Heterogeneous Resource Management.
© 2007 Xilinx, Inc. All Rights Reserved This material exempt per Department of Commerce license exception TSU Hardware Design INF3430 MicroBlaze 7.1.
טכניון – מכון טכנולוגי לישראל הפקולטה להנדסת חשמל PowerPC based reliable computer Students:Guy Derry Gil Wiechman Instructor: Isaschar Walter Winter 2003.
NIOS II Ethernet Communication Final Presentation
LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.
1 EDK 7.1 Tutorial -- SystemACE and EthernetMAC on Avnet Virtex II pro Development Boards Chia-Tien Dan Lo Department of Computer Science University of.
Peter JansweijerATLAS week: February 24, 2004Slide 1 Preparatory Design Studies MROD-X Use Xilinx Virtex II Pro –Rocket IO –Power PC –Port the current.
© 2003 Xilinx, Inc. All Rights Reserved System Simulation.
© 2004 Xilinx, Inc. All Rights Reserved Embedded Processor Design.
Wang-110 D/MAPLD SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA Mandy M. Wang JPL R&TD Mobility Avionics.
© 2004 Xilinx, Inc. All Rights Reserved EDK Overview.
Final Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The.
Final Presentation DigiSat Reliable Computer – Multiprocessor Control System, Part B. Niv Best, Shai Israeli Instructor: Oren Kerem, (Isaschar Walter)
A Monte Carlo Simulation Accelerator using FPGA Devices Final Year project : LHW0304 Ng Kin Fung && Ng Kwok Tung Supervisor : Professor LEONG, Heng Wai.
This material exempt per Department of Commerce license exception TSU Xilinx On-Chip Debug.
© 2004 Xilinx, Inc. All Rights Reserved Adding a Processor System to an FPGA Design.
© 2003 Xilinx, Inc. All Rights Reserved Course Wrap Up DSP Design Flow.
Peter JansweijerATLAS week: February 24, 2004Slide 1 Preparatory Design Studies MROD-X Use Xilinx Virtex II Pro –RocketIO –PowerPC –Port the current MROD-In.
Survey of Reconfigurable Logic Technologies
System on a Programmable Chip (System on a Reprogrammable Chip)
Programmable Logic Devices
Using FPGAs with Processors in YOUR Designs
Course Agenda DSP Design Flow.
ChipScope Pro Software
Lab3 Adding Custom IP Lab: MicroBlaze
ChipScope Pro Software
Presentation transcript:

Part A Presentation Implementation of DSP Algorithm on SoC Student : Einat Tevel Supervisor : Isaschar Walter Accompanying engineer : Emilia Burlak The project is conducted with cooperation of Rafael. winter 2003/2004

Project Goals - Review Studying and investigating the architecture of System on Programmable Chip (SoC). Studying and investigating the architecture of System on Programmable Chip (SoC). Deciding on the Software/Hardware partition to be implemented. Deciding on the Software/Hardware partition to be implemented. Implementing a signal processing algorithm on the chosen platform. Implementing a signal processing algorithm on the chosen platform. First Semester: Full understanding of the elements and studied environments. Full understanding of the elements and studied environments. Writing and Running examples on the evaluation board. Writing and Running examples on the evaluation board.

Project Schedule Second Part of First Semester Project Schedule Second Part of First Semester Studying the PowerPC processor. Studying the PowerPC processor. Studying the EDK software for developing SoC. Studying the EDK software for developing SoC. Studying the SoC design process. Studying the SoC design process. Get familiar with the Xilinx ’ s evaluation board. Get familiar with the Xilinx ’ s evaluation board. Writing and Running examples on the evaluation Writing and Running examples on the evaluation board. board.

System View PowerPC 405 Core I-Cache D-Cache CoreConnect Processor Local Bus (PLB) User Logic External Memory High Speed Peripherals CoreConnect On-Chip Peripheral Bus (OPB) Low Speed Peripherals PLB-OPB Bridge FPGA Block RAM

Implementation Tools EDK - Embedded Development Kit EDK - Embedded Development Kit Provides a set of design tools and a wide selection of standard peripherals required to build embedded processor systems. Provides a set of design tools and a wide selection of standard peripherals required to build embedded processor systems. XPS (Xilinx Platform Studio) – Provides an integrated environment for creating the software and hardware specification flows. XPS (Xilinx Platform Studio) – Provides an integrated environment for creating the software and hardware specification flows. Standard peripherals (GPIO, SDRAM, Clock Modules, Ethernet). Standard peripherals (GPIO, SDRAM, Clock Modules, Ethernet). GNU based software tools (C compiler, assembler, linker and debugger). GNU based software tools (C compiler, assembler, linker and debugger). Virtex-II Pro FF1152 Development Board Virtex-II Pro FF1152 Development Board Enables implementation of embedded processor based applications using IP cores and customized modules. Enables implementation of embedded processor based applications using IP cores and customized modules. Virtex II Pro FPGA (XC2VP30). Virtex II Pro FPGA (XC2VP30). Two Integrated PowerPC Processors. Two Integrated PowerPC Processors. Two memory blocks of 8Mx32 SDRAM memory each. Two memory blocks of 8Mx32 SDRAM memory each.

Virtex-II Pro FF1152 Development Board

CoreConnect Architecture Elements of the CoreConnect architecture: PLB (Processor Local Bus): high performance synchronous bus designed for connection of processors to high-performance peripherals devices. OPB (On-chip Peripheral Bus): general-purpose synchronous bus designed for connection of on-chip peripheral devices.

User Cores Objective: Add a User Core to an embedded system, which implements a user-logic written in vhdl. Objective: Add a User Core to an embedded system, which implements a user-logic written in vhdl. The User core is to be attached to an embedded processor bus, such as OPB or PLB. The User core is to be attached to an embedded processor bus, such as OPB or PLB. There are several configurations that can be used to connect user cores and user logic to an embedded subsystem. There are several configurations that can be used to connect user cores and user logic to an embedded subsystem.

Connecting User Cores IPIF (IP Interface) – a portable, pre-designed bus interface, that takes care of the bus interface signals, bus protocol and other interface issues. The IPIF presents an interface to the user logic called the IP InterConnect (IPIC). User logic is a logic that has been designed with an IPIC interface to make use of the IPIF bus attachment and other services. User logic that is designed with an IPIC has the advantage that it is portable and can be easily reused on different processor buses by changing the IPIF to which it is attached.

IPIF Scheme

User Core Reference Design simplifies the task of attaching the IPIF to user logic. The user core reference design is a VHDL file that instantiates the IPIF and provides most of the VHDL code required to create a user core. The reference design provides a place to instantiate the user logic, which can be VHDL or a black box created from verilog, schematic, etc.

User Core Reference Design Scheme

IPIF Example

Components - Hardware PPC 405 PPC 405 Plb2Opb Bridge Plb2Opb Bridge OPB OPB Uartlite : RS232 Uartlite : RS232 GPIO: LEDs GPIO: LEDs GPIO: Push Buttons GPIO: Push Buttons GPIO: DIPs GPIO: DIPs SDRAM (8M*32) SDRAM (8M*32) PLB PLB User Core User Core Bram Bram System DCM System DCM System RESET System RESET

User Logic Receives 1 of 4 addresses ( “ 00 ”, ” 01 ”, ” 10 ”, ” 11 ” ). Receives 1 of 4 addresses ( “ 00 ”, ” 01 ”, ” 10 ”, ” 11 ” ). Each address correspond to a LED. Each address correspond to a LED. The appropriate LED is turned on/off according to the LSB of the data. The appropriate LED is turned on/off according to the LSB of the data. The data returned is the data received + const, when const is determined by each address. The data returned is the data received + const, when const is determined by each address. ( “ 00 ” : c=0, ” 01 ” : c=1, “ 10 ” : c=2, “ 11 ” :c=3) “ 10 ” : c=2, “ 11 ” :c=3) Bus2IP_Addr Bus2IP_Clk Bus2IP_CS Bus2IP_Data Bus2IP_RdCE Bus2IP_Reset Bus2IP_WrCE IP2Bus_ Data LED User Logic 1 bit 4 bit 32 bit

User Logic – VHDL (sample) addr <= Bus2IP_Addr(28 to 29); … if Bus2IP_CS = '1' and Bus2IP_WrCE = '1 ‘ then data <= Bus2IP_Data(24 to 31); data <= Bus2IP_Data(24 to 31); case addr is case addr is when "00" => led0 led0 <= Bus2IP_Data(31); when "01" => led1 led1 <= Bus2IP_Data(31); when "10" => led2 led2 <= Bus2IP_Data(31); when "11" => led3 led3 <= Bus2IP_Data(31); when others => null; when others => null; end case; end case; end if; ….

Software – main int main(){ Xuint32 Data=0, Res=0; Xuint32 Data=0, Res=0; Xio_Address addr; Xio_Address addr; unsigned int usec_time=50000; unsigned int usec_time=50000; xil_print( “ ***MY OPB-PLB USER LOGIC*** ” ); xil_print( “ ***MY OPB-PLB USER LOGIC*** ” ); check_sdram(); //calling check_sdram function check_sdram(); //calling check_sdram function check_leds(); //calling check_leds function check_leds(); //calling check_leds function addr=(Xio_Address)XPAR_PLB_USER_CORE_0_BASEADDR; addr=(Xio_Address)XPAR_PLB_USER_CORE_0_BASEADDR; while(1){ while(1){ Xio_Out32(addr, Data); Xio_Out32(addr, Data); usleep(1); usleep(1); Res=XIo_In32(addr); Res=XIo_In32(addr); xil_printf( “ Res=%d\n\r ”, Res); xil_printf( “ Res=%d\n\r ”, Res); usleep(usec_time); usleep(usec_time); }}

Software – Memory Check Function void check_sdram(){ … temp=sdram_location; temp=sdram_location; // writing to all the memory addresses // writing to all the memory addresses for(loop_count=0;loop_count<mem_size;loop_count++){ for(loop_count=0;loop_count<mem_size;loop_count++){ *sdram_location = loop_count; sdram_location++; sdram_location++; } sdram_location=temp; sdram_location=temp; // reading from all the memory address and comparing to expacted // reading from all the memory address and comparing to expacted for(loop_count=0;loop_count<mem_size;loop_count++){ for(loop_count=0;loop_count<mem_size;loop_count++){ sdram_data_read = *sdram_location; if(sdram_data_read!=loop_count) // failure – printing and exiting else sdram_location++ } xil_printf("SDRAM Test Passed\n\r"); xil_printf("SDRAM Test Passed\n\r");}

Software – LEDs Check Function void check_leds(){ … XGpio_mSetDataDirection(XPAR_LEDS_4BIT_BASEADDR, 0x00); XGpio_mSetDataDirection(XPAR_LEDS_4BIT_BASEADDR, 0x00); for (count=0; count < 16; count++) { for (count=0; count < 16; count++) { XGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDR, ~count); XGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDR, ~count); usleep(100000); usleep(100000); xil_printf("Leds Count=%d\n\r",count); } xil_printf("LEDS Test Passed\n\r"); xil_printf("LEDS Test Passed\n\r");}

Output

Comments The VHDL code was tested using ModelSim. The VHDL code was tested using ModelSim. Environment Testing – Using LEDs. Environment Testing – Using LEDs. The Evaluation Board is new, therefore required adjustments in the UCF file. The Evaluation Board is new, therefore required adjustments in the UCF file. Other Debug tools, such as Chip-Scope, where not used. Other Debug tools, such as Chip-Scope, where not used.

Other Examples Running Xilinx ’ s examples: Running Xilinx ’ s examples: Basic Components (GPIO). Basic Components (GPIO). Additional Memory. Additional Memory. 2 PowerPCs. 2 PowerPCs. IPIF example of LEDs Brightness. IPIF example of LEDs Brightness. User Logic: User Logic: On OPB On OPB On PLB On PLB

Goals – Second Part Implementing a signal processing algorithm based on a FIR/IIR Filter with Programmable coefficients. Implementing a signal processing algorithm based on a FIR/IIR Filter with Programmable coefficients. Simulating and checking the code of the algorithm in hardware and software. Simulating and checking the code of the algorithm in hardware and software. Running the algorithm on the board. Running the algorithm on the board.

Project schedule second semester 1 st week: Defining the algorithm to be implemented. Defining the algorithm to be implemented. 2 nd -3 rd week: Design of the algorithm – block scheme. Design of the algorithm – block scheme. 4 th week: Dividing the workload Software/Hardware and Estimating the FPGA ’ s volume. Dividing the workload Software/Hardware and Estimating the FPGA ’ s volume. 5 th -6 th week: Detailed design of each block from the scheme. Detailed design of each block from the scheme.

Project schedule second semester (cont) 7 th -9 th week: Hardware implementation Hardware implementation Software implementation. Software implementation. 10 th -end: Simulation Simulation Synthesis Synthesis Checking the algorithm using the evaluation board. Checking the algorithm using the evaluation board.

Thank You