© 2010 Altera Corporation—Public Modeling and Simulating Wireless Systems Using MATLAB ® and Simulink ® 2010 Technology Roadshow

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Agenda Introduction  Challenges of wireless system modeling and simulation  Introduction to MATLAB, Simulink, and blocksets Models and demonstrations  System-level wireless system model  RF receiver front-end design  Fixed-point design  HDL co-simulation Next steps  FPGA implementation 2

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Design Flow Challenges Result in High Verification Costs Design and Implementation Research & System Level Design Requirements Algorithms Integration and Test Analog Hardware Embedded Software Digital Hardware VHDL, VerilogSPICEC/C++ Gap #1: Algorithm development is not connected to the design flow. Gap #1: Algorithm development is not connected to the design flow. Gap #2: Multiple tools are used for design and implementation. Gap #2: Multiple tools are used for design and implementation. Impact: Errors are found too late; product is delayed. Impact: Errors are found too late; product is delayed. 3

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. System Design Requires Multi-Domain Expertise and Collaboration Signal modeling in three domains:  Time domain  Frequency domain  Spatial domain System modeling in three domains:  Digital baseband  Analog/mixed-signal  Radio frequency Advanced Multifunction RF Concept (AMRFC) Test-Bed Block Diagram (radar- 4

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Requirements Solution: Multi-domain Modeling and Simulation Unify algorithm research, design, & testing 1. Model the system and requirements in the same industry-standard environment. 2. Model different subsystem domains in one integrated environment. 3. Re-use this model as a testbench throughout the design process 4. Verify implementation details using system testbench and co- simulation with your chosen design tools. 5. Leverage the environment all the way to integration and test. Design Analog/RF Models Environment Models Algorithms Digital Models Timing and Control Logic Integration and Test Test Environments C, C++VHDL, Verilog Embedded Software Prototype SPICE Digital Hardware Analog Hardware Implementation Generate 5

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Simulink Key Features Hierarchical, component-based modeling MATLAB ® integration Extensive library of predefined blocks Application-specific libraries available Open application program interface (API) 6

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Key Features – Signal Processing Blockset Waveform coding Matched filter detectors Adaptive beamforming or detection (STAP) DOA, target detection Beamforming Tracking N-dimensional signals 7

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Key Features – Communications Blockset Modulation Sequence generators RF impairments Channel models 8

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Key Features – RF Blockset Complex baseband-equivalent modeling Physical blocks account for reflections Cascaded receiver chains: gain, noise figure, IP3 modeling Verify RF behavior at system level Amplifiers, filters, mixers, etc. 9

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Demonstrations 10

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. RF Receiver Front End – Conclusion Radar is a mixed domain of signal processing and RF RF engineers can specify performance of RF components with basic specs like gain and noise figure for first pass modeling RF engineers can model at a higher level of fidelity by using measured performance data for RF components 11

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Fixed-Point Design Signal processing engineers face many decisions: Implement in time or frequency domain? Word length needed for fixed-point processing? Protect against overflow? Problem statement: Need to perform what-if trades at the implementation level and at the bit level 12

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Example: Digital Down Converter for Radar System Diplex DUC Pulse train/ compress LO Mixer Format Pre- filter Beam weight IFFT RF Format Spatial estimate Correlate Track/ predict Threshold Decision making Post-processingPre-processing Beam weight process FPGA implementation High-speed serial Front end High-speed serial Example design focus Pre- detect Beam weight process DDC FFT 13

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. ADC Traditional Digital Downconversion Complex NCO M:1 Decimating Low Pass FIR I Baseband Data Q Baseband Data X Real IF Data exp ( j θ k n + PhsAdj) Baseband Fc = Carrier Signal Frequency, FBaseband Carrier Signal Frequency, F Real IF Signal Complex Baseband Signal 14

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Polyphase Digital Downconversion 350 MSPS 1:2 Demux exp ( j ω carrier +0+PhsAdj) exp ( j ω carrier +π+PhsAdj) NCO X X 8:1 Decimating FIR 1:2 Demux exp ( j ω carrier +π/4+PhsAdj) exp ( j ω carrier +5π/4+PhsAdj) NCO X X 8:1 Decimating FIR 1:2 Demux exp ( j ω carrier + π/2 +PhsAdj) exp ( j ω carrier + 3π/2 + PhsAdj) NCO X X 8:1 Decimating FIR 1:2 Demux exp ( j ω carrier +3 π/4 +PhsAdj) exp ( j ω carrier +7π/4+PhsAdj) NCO X X 8:1 Decimating FIR baseband I data baseband Q data ADC 2.8 GSPS 15

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. ADC Aliased Polyphase Digital Downconversion Real IF Data Baseband Fc = Carrier Signal FS/2 K=2 for second Nyquist zone FS Real IF Signal Spinner selects Nyquist Zone to downconvert Low Pass FIRФ 1 exp ( j 1k 2π/8) X Low Pass FIRФ 2 exp ( j 2k 2π/8) X Low Pass FIRФ 3 exp ( j 3k 2π/8) X Low Pass FIRФ 4 exp ( j 4k 2π/8) X Low Pass FIRФ 5 exp ( j 5k 2π/8) X Low Pass FIRФ 6 exp ( j 6k 2π/8) X Low Pass FIRФ 7 exp ( j 7k 2π/8) X baseband I data baseband Q data Low Pass FIRФ 0 exp ( j 0k 2π/8) X + X 350 MSPS Optional Complex NCO 16

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. What We Used Simulink Embedded MATLAB RF Blockset Signal Processing Blockset Fixed-Point Tool EDA Simulator Links Masked subsystems and libraries 17

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Key Take-Aways Integrated tool for collaboration among multiple engineering teams:  System engineers  Signal processing engineers  Antenna designers  RF engineers  HDL programmers Environment to explore design tradeoffs:  Fixed-point processing  RF receiver architecture  Beam-forming configurations Continuous verification flow from system- level specifications to implementation- level component designs MATLAB ® and Simulink ® provide: 18

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. Next steps: FPGA implementation The original Simulink floating-point model and the elaborated fixed-point models are re-used as a system level verification test bench Verification “deltas” resulting from device-specific behavior are evaluated using system level metrics (BER, Pd, etc.) Altera ® Advanced DSP Builder blocks enable system level verification by maintaining the connection between high level model and FPGA hardware 19

© 2010 Altera Corporation—Public ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. For More Information about MATLAB Products or Services, Please Contact: Mainland, China Non-military Industry and Education Users: The MathWorks China Website: Tel: Military Industry Users: HiRain Technologies Website: Tel: Hong Kong/ Macau World Express Computer Systems Ltd. Tel: Taiwan TeraSoft Inc. Website: Tel: US Headquarters ： The MathWorks, Inc Website: Tel:

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