ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU Undergraduate Projects Speaker: Wes Adviser: Prof. An-Yeu Wu Date: 2015/09/22 Lab homepage: (slide 會放在網頁 )

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P2 Idea Design IC Design and Implementation

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P3 Architecture Level Chip Algorithm Level FFT- From Algorithm to Architecture & Chip Architecture Mapping Fixed-Point Analysis HDL: Verilog Synthesis Layout Data Flow >>fft(x);

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P4 Cell-based Design Flow Verilog RTL Coding Functional simulation & Verification Logic Synthesis Physical Layout Tech. file Verilog test bench SoC Encounter IC Compiler Pyhsical Design & Implementation Design CompilerSynthesis NCverilog VCS Simulation Text EditorVerilog Design Tools Design Stage Specification (FFT Algorithm) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. (Mapping, Placing & Routing) Spec. Modelling Matlab or C++ sdc Chip Focus!!

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P5 Verilog HDL  HDL – Hardware Description Language  Why use an HDL  Hardware is becoming very difficult to design directly  HDL is easier and cheaper to explore different design options  Reduce design time and cost  Goal  HDL has high-level programming language constructs and constructs to describe the connectivity of your circuit  Ability to mix different levels of abstraction freely  One language for all aspects of design, test, and verification

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P6 Project Goal  Architecture Design & Fixed-Point Analysis  Front-End Digital IC Design Flow Training  Behavioral Modeling: C or Matlab  Hardware Description Language: Verilog  Design Issue:  Application  UWB System  Biomedical Applications  Different Architectures of FFT  Pipelined FFT  Memory-based FFT  Speed 、 Area and Power

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P7 Midterm: Fix-Point Analysis Optimal set: 2+6 = 8 Integer 2 bits Fractional 6 bits Algorithm Level Architecture Level Fixed-Point Analysis Chip HDL: Verilog & Synthesis

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P8 Final: Hardware Implementation Algorithm Level Architecture Level Chip HDL: Verilog & Synthesis Fixed-Point Analysis

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P9 FFT  適合對象  對 Digital IC Design 有興趣的同學  條件  Switch Logic Circuits, VLSI Design and Signal and System  內容  Skills for Research  Paper Reading  Presentation  Skills for Digital System Design  Digital IC Design Flow : Verilog Coding  Synthesis  Design Flow for DSP Architecture Mapping, Design, and Verification  Behavioral Modeling and Fixed-Point Analysis: C or Matlab

ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU P10 Contact Information  Feel free to contact with 吳安宇教授  Office: 電機二館 441 室， Phone:(02)   直接連絡 Access IC Lab 學長  實驗室 : 電機二館， Room 232 (EE2-232)  Phone: (02) , ext.232  李懷霆 :  Lab Website 