An 800-MHz Embedded DRAM With a Concurrent Refresh mode Toshiaki Kirihata, Senior Member, IEEE, Paul Parries, David R. Hanson, Hoki Kim, Member, IEEE, John Golz, Gregory Fredeman, Raj Rajeevakumar, Member, IEEE, John Griesemer, Norman Robson, Alberto Cestero, Babar A. Khan, Geng Wang, Member, IEEE, Matt Wordeman, Senior Member, IEEE, and Subramanian S. Iyer, Fellow, IEEE IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 6, JUNE 2005

Highlights Size:256 Mb Cell Size : Cell Area : External IO Voltage : 1.5V Word line material: CoSi 2 (Cobalt Silicide) Banks: 16 Embedded DRAM High performance cell 2.2nm Gate oxide Concurrent Refresh Mode Concurrent Refresh Scheduler Command Multiplier for 800MHz memory frequency.

2.High Performance Cell Scaling of the cell is achieved by reducing the gate oxide thickness to 2.2nm. 10% Cell size reduction over the conventional memory cell (Gate-oxide thickness:5.2nm). Enables use of reduced voltages in memory cell and the wordline driver Disadvantage: Results in short data retention time of For example a 4 Mb memory having 8K wordlines, requires 8K refresh cycles within,this will require one refresh command in 8 ns, resulting in 0% memory available for an 8ns memory cycle. Solution: Refresh more cells per refresh command by activating multiple wordlines, which requires more current. 25% increase in current is observed by lower threshold, shorter channel, and thinner oxide. Integrates a DRAM on the same die with microprocessor. 1.Embedded DRAM

Concurrent Refresh Mode Refreshes memory by bank select signal while concurrently enabling the memory access operation. For 16 banks, we have two sets of ports BSEL 0-15 : o Memory access operation. o Each port activates the corresponding array Bank 0-15 RBSEL 0-15 : o Refresh operation. o Refresh bank select ports activate the corresponding array independent from memory access operation. oThe addresses BSEL 0-15 and RBSEL 0-15 are fetched at the clock edge along with read and write signals. oCorrect management of BSEL 0-15 and RBSEL 0-15 can give % memory utilization.

Concurrent Refresh Mode - Architecture

Concurrent Refresh Scheduler Examines the incoming memory access addressing. Decides which bank to refresh. Two shift registers (up - count and down-count) are used to identify two memory banks to refresh. (FU & FD) To avoid contention with memory access operation the each bit from the ‘OR’ is gated with a BSEL. When BSEL is high RBSEL is blocked.

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