SSV Summit November 2013 Cadence Tempus™ Timing Signoff Solution

2© 2013 Cadence Design Systems, Inc. All rights reserved Signoff closure up to 40% of the design flow Need faster runtimes Capacity for +100M cell designs with 100s of timing views Better accuracy to reduce pessimism, power, area Industry needs for n ext g eneration signoff

3© 2013 Cadence Design Systems, Inc. All rights reserved The Tempus™ Timing Signoff Solution Tempus – It’s about TIME Up to 10X reduction in closure time Placement and routing aware Unlimited MMMC capacity Massively parallelized computation Scalable to 100s of CPUs Optimized data structures Up to 10X faster path-based analysis (PBA) Advanced process modeling TSMC-certified accuracy

4© 2013 Cadence Design Systems, Inc. All rights reserved Optimized multi-threading Distributed processing Incremental & hierarchical analysis Concurrent multi-mode multi- corner analysis Parallelized path based analysis Performance background Stacked performance enablement MMMC Concurrency MMMC Concurrency Incremental Analysis Distributed Processing Flat Single View (Multi-Threading) Technology

5© 2013 Cadence Design Systems, Inc. All rights reserved Combines multi-threading with distribution Simple setup –User specifies desired resources Parallelization transparent to user Up to 50M cells analyzed in one hour Low memory footprint Performance metrics Parallelized processing MMMC Concurrency MMMC Concurrency Incremental Analysis Distributed Processing Flat Single View (Multi-Threading)

6© 2013 Cadence Design Systems, Inc. All rights reserved Analyzes all modes and corners in one timing session Runs on one compute server More than 2X faster with same hardware –Less than 20% memory overhead per additional timing view Reduces hardware resource requirement Concurrent MMMC view analysis MMMC Concurrency MMMC Concurrency Incremental Analysis Distributed Processing Flat Single View (Multi-Threading)

7© 2013 Cadence Design Systems, Inc. All rights reserved Graph based analysis is fast but inherently pessimistic Path based analysis is slow but reduces pessimism –Accurate transitions and derates Tempus solves PBA reporting runtimes –Parallelized computation Path-based analysis (PBA) Reduced pessimism and runtime Pessimism reduction Pessimism reduction

8© 2013 Cadence Design Systems, Inc. All rights reserved Full timing/optimization solution Delay and SI Distributed MMMC Physically aware Setup/hold/DRV/leakage optimization –Path or graph based Tempus timing closure Tempus Distributed MMMC delay calculation and STA Distributed MMMC delay calculation and STA Physically- aware optimization Hold, DRV, setup, leakage Physically- aware optimization Hold, DRV, setup, leakage Place and route Timing closed 2-3 Iteration Physical view (LEF/ DEF) Physically aware ECO

9© 2013 Cadence Design Systems, Inc. All rights reserved. Tempus resonates with users What we said… Community feedback (courtesy of DeepChip)…

10© 2013 Cadence Design Systems, Inc. All rights reserved Presented at ARM® TechCon 2013 Cortex®-A12 testchip –28nm SLP Technology Close collaboration –ARM, Global Foundries, Cadence Full Cadence flow –Final signoff with Tempus! Key Tempus technologies –MMMC analysis –Physically aware optimization Global Foundries tapeout success

11© 2013 Cadence Design Systems, Inc. All rights reserved. Cadence is solving the design complexity challenge –Eliminating the signoff bottleneck –Enables power, performance and time-to-market goals Tempus™ accelerates timing analysis and closure by weeks –As much as 10x faster –Handles 100’s of millions of cells –Optimizes timing across hundreds of views Strong customer demand –Multiple evaluations and customers Early tapeout success In summary More to come!

12© 2013 Cadence Design Systems, Inc. All rights reserved "Cadence, Encounter, Tempus, Virtuoso and the Cadence logo are trademarks of Cadence Design Systems, Inc. All other trademarks and logos are the property of their respective holders."