October 10, 20001

2 USB 2.0 Technical Overview Brad Hosler USB Engineering Manager Intel Corporation

October 10, Conference Goal w Provide you with the information you need to build USB 2.0 products – USB 2.0 technical details – USB 2.0 Infrastructure – Building USB 2.0 devices – USB 2.0 Building Blocks

October 10, USB 2.0: Conference Agenda w Architecture Overview w Peripheral Development Enabling w USB 2.0 Compliance and Logo Program w USB 2.0 Compliance Testing Single Track: Topics for Everyone

October 10, Split Track: Focused Topics USB 2.0: Technical Agenda w USB2 Specifications – Electricals – Protocol – Hubs w Power Management w Host Controller Spec w Cable Testing w USB “On the Go” w USB2 Software – MS Roadmap – Driver Testing – HS Isoch Interface w Building USB2 Devices – Design Options – Transceiver Macrocell – Firmware and Testing – Analyzers w Platform Design – BIOS

October 10, Architecture Overview

October 10, USB 2.0: What Changed?? w Low level electricals for High Speed (HS) signaling – Much higher bit rate (480Mb/s) requires new transmitter/receiver w Hub changes for backward compatibility – Features limit bandwidth impact of Full Speed (FS) and Low Speed (LS) devices on HS devices – FS/LS devices consume a bit-rate equivalent of HS bandwidth

October 10, USB 2.0: What Didn’t Change? w Same host/device model – Host is in charge – Devices are inexpensive w Same basic protocol – Token, data, handshake w Same device framework – Descriptors w Same software interfaces – USBDI

October 10, USB 2.0: What Didn’t Change? w Same power distribution and consumption – 500ua suspend, 100ma unconfigured, 500ma configured w Same power management features – Suspend/resume model unchanged w Same topology management – Hub features to handle connect, disconnect, enable, disable, … w Same cables and connectors Continued

October 10, System SW Client Driver USB 1.1 Hub USB 1.1 Device HS Hub USB 1.1 Hub USB 1.1 Device HS Device USB 2.0 Host Controller Controller Full/Low Speed High Speed Only (2 x 12Mb/s Capacity) Sample USB 2.0 Topology w Hub provides high-speed expansion (ala USB 1.1 hub) w Hub provides additional Full/Low speed bus(es)

October 10, USB 2.0 Host Controller w Allows port functionality regardless of OS version – USB 1.1 OS will ‘just work’ as USB 1.1 ports w USB 1.1 HCs can go away over time – Replaced with integrated USB 2.0 Hub USB 2.0 Host Controller (HC) Port 1 USB 1.1 USB 1.1HCs High-Speed Mode (Enhanced Interface) USB HC Port 1Port 2 Port Owner Control(s) Port 1Port 2 Port Routing Logic Port N HC Control Logic/Data Buffering Enhanced HC Control Logic Enhanced Data Buffering Port 2Port N

October 10, USB 2.0 Hub w Hub controller same as USB1.1 w Routing logic connects device to appropriate path High Speed only Full/LowSpeed Routing Logic Port TransactionTranslatorTransactionTranslator HS Signal Repeater Repeater HubControllerHubController

October 10, Transaction Translator (TT) w TT handles low/full speed transactions – Driven with split transactions w Start-Split – Host tells Hub to initiate full/low speed transaction w Complete-Split – Host asks Hub for results of previous full/low speed transaction

October 10, Bandwidth Usage w Low/full speed devices use bit-rate equivalent of USB2.0 bandwidth – 6Mbps classic camera (50% of classic) uses less than 2% of USB2.0 bandwidth (6Mbps/480Mbps)

October 10, ISOCH IN Through a TT HS Bus Full Speed Bus uSOF 1ms uSOFuSOFuSOFuSOFuSOFuSOFuSOFuSOF SOFSOF SS SS = Start Split CSCSCSCS 125us CS = Complete Split

October 10, Demo: Full Speed Device w Show the split transactions w Show better performance behind USB 2.0 hub than behind USB 1.1 HC

October 10, Summary w Two major changes for USB 2.0 – Higher speed electricals – Transaction translator in USB2.0 hub w Backward compatibility – Has little impact on HS bandwidth – May even improve FS performance