MonolithIC 3D Inc., Patents Pending MonolithIC 3D ICs October MonolithIC 3D Inc., Patents Pending

The Monolithic 3D Innovation  Utilize Ion-Cut (‘Smart-Cut’) to transfer a thin (<100nm) single crystal layer on top of the bottom (base) wafer  Form the cut at less than 400ºC *  Use co-implant  Use mechanically assisted cleaving  Form the bonding at less than 400ºC * * See details at: Low Temperature Cleaving, Low Temperature Wafer Direct BondingLow Temperature CleavingLow Temperature Wafer Direct Bonding  Split the transistor processing to two portions  High temperature process portion (ion implant and activation) to be done before the Ion-Cut  Low temperature (<400°C) process portion (etch and deposition) to be done after layer transfer See details in the following slides:

Monolithic 3D ICs Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (millions of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow:SmartCut Soitec’s Smart Cut Patented* Flow: MonolithIC 3D Inc., Patents Pending 3 *Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012

Monolithic 3D ICs Ion cuttingIon cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in-effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick. MonolithIC 3D Inc., Patents Pending 4

Figure 3 Using ion-cutting to place a thin layer of monocrystalline silicon above a processed (transistors and metallization) base wafer MonolithIC 3D Inc., Patents Pending 5 p- Si Oxide p- Si Oxide H Top layer Bottom layer Oxide Hydrogen implant of top layer Flip top layer and bond to bottom layer Oxide p- Si Oxide H Cleave using <400 o C anneal or sideways mechanical force. CMP. Oxide Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today p- Si

MonolithIC 3D Inc. Patents Pending 6 Chapter 3 Monolithic 3D HKMG

MonolithIC 3D Inc. Patents Pending 7 The monolithic 3D IC technology is applied to produce monolithically stacked high performance High-k Metal Gate (HKMG) devices, the world’s most advanced production transistors. 3D Monolithic State-of-the-Art transistors are formed with ion-cut applied to a gate-last process, combined with a low temperature face-up layer transfer, repeating layouts, and an innovative inter-layer via (ILV) alignment scheme. Monolithic 3D IC provides a path to reduce logic, SOC, and memory costs without investing in expensive scaling down. Technology

MonolithIC 3D Inc. Patents Pending 8 ~700µm Donor Wafer On the donor wafer, fabricate standard dummy gates with oxide and poly-Si; >900ºC OK PMOS NMOS Silicon Poly Oxide

MonolithIC 3D Inc. Patents Pending 9 ~700µm Donor Wafer Form transistor source/drain PMOS NMOS Silicon Poly Oxide

MonolithIC 3D Inc. Patents Pending 10 ~700µm Donor Wafer PMOSNMOS Silicon Form inter layer dielectric (ILD), S/D implants and high temp anneals, CMP to transistor tops CMP to top of dummy gates ILD S/D Implant

MonolithIC 3D Inc. Patents Pending 11 ~700µm Donor Wafer PMOSNMOS Silicon Implant hydrogen to generate cleave plane

MonolithIC 3D Inc. Patents Pending 12 ~700µm Donor Wafer PMOSNMOS Silicon Implant hydrogen to generate cleave plane

MonolithIC 3D Inc. Patents Pending 13 ~700µm Donor Wafer PMOSNMOS Silicon Implant hydrogen to generate cleave plane H+

MonolithIC 3D Inc. Patents Pending 14 ~700µm Donor Wafer Silicon Bond donor wafer to carrier wafer H+ ~700µm Carrier Wafer

MonolithIC 3D Inc. Patents Pending 15 ~700µm Donor Wafer Cleave to remove bulk of donor wafer H+ ~700µm Carrier Wafer Transferred Donor Layer Silicon

MonolithIC 3D Inc. Patents Pending 16 CMP to STI ~700µm Carrier Wafer STI Transferred Donor Layer

MonolithIC 3D Inc. Patents Pending 17 Deposit oxide, ox-ox bond carrier structure to base wafer that has transistors & circuits ~700µm Carrier Wafer STI Oxide-oxide bond PMOS NMOS Transferred Donor Layer Base Wafer

18 Remove carrier wafer Oxide-oxide bond ~700µm Carrier Wafer Transferred Donor Layer MonolithIC 3D Inc. Patents Pending PMOS NMOS Base Wafer

19 Carrier wafer had been removed Oxide-oxide bond Transferred Donor Layer MonolithIC 3D Inc. Patents Pending PMOS NMOS Base Wafer

20 Replace dummy gate stacks with Hafnium Oxide & metal at low temp Oxide-oxide bond Transferred Donor Layer MonolithIC 3D Inc. Patents Pending PMOS NMOS Base Wafer Note: Replacing oxide and gate result in oxide and gate that were not damaged by the H+ implant

21 Form inter layer via through oxide only (similar to standard via) Oxide-oxide bond Transferred Donor Layer MonolithIC 3D Inc. Patents Pending PMOS NMOS Base Wafer Note: The second mono-crystal layer is very thin (<100nm) and via through it, is similar to other vias in the metal stack

MonolithIC 3D Inc. Patents Pending 22 Form top layer interconnect and connect layers with inter layer via Oxide-oxide bond Transferred Donor Layer MonolithIC 3D Inc. Patents Pending PMOS NMOS Base Wafer ILV

MonolithIC 3D  Inc. Patents Pending 23 Novel Alignment Scheme using Repeating Layouts  Even if misalignment occurs during bonding  repeating layouts allow correct connections.  Above representation simplistic (high area penalty). Bottom layer layout Top layer layout Landing pad Through- layer connection Oxide

MonolithIC 3D  Inc. Patents Pending 24 Smart Alignment Scheme Bottom layer layout Top layer layout Landing pad Through- layer connection Oxide