Computer Architecture Chapter 5 Fall 2005 Department of Computer Science Kent State University

Our implementation of the MIPS is simplified –memory-reference instructions: lw, sw –arithmetic-logical instructions: add, sub, and, or, slt –control flow instructions: beq, j Generic implementation –use the program counter (PC) to supply the instruction address and fetch the instruction from memory (and update the PC) –decode the instruction (and read registers) –execute the instruction All instructions (except j ) use the ALU after reading the registers How? memory-reference? arithmetic? control flow? The Processor: Datapath & Control Fetch PC = PC+4 DecodeExec

Two types of functional units: –elements that operate on data values (combinational) –elements that contain state (sequential) Abstract / Simplified View

More Implementation Details

Fetching Instructions Fetching instructions involves –reading the instruction from the Instruction Memory –updating the PC to hold the address of the next instruction Read Address Instruction Memory Add PC 4 –PC is updated every cycle, so it does not need an explicit write control signal –Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal

Fetch-Decode-Execute In order to execute an instruction we must –Fetch the instruction from memory –Determine what the instruction is (decode) –Execute it Fetch and decode are the same for all instructions Execute depends on the type of instruction

Instruction Formats oprsrtrdshamtfunct 31:2625:2120:1615:1110:65:0 oprsrtimmed 31:2625:2120:1615:0 opaddr 31:2625:0

Decoding Instructions Decoding instructions involves –sending the fetched instruction’s opcode and function field bits to the control unit Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 Control Unit –reading two values from the Register File Register File addresses are contained in the instruction

Executing Load and Store Load –Fetch operand (base address) from register –Compute effective address –Read data from memory –Write result back to register Store –Fetch operands from registers –Compute effective address –Write data to memory

Executing Arithmetic/Logic Arithmetic/logic (add, sub, and, or, slt) –Fetch operands from registers –Perform operation –Write result back to register

Executing Branch and Jump Conditional branch (beq) –Fetch operands from registers –Compare operands –If equal add displacement to PC Jump (j) –Write new value to PC

ALU Instructions Components –Register File –ALU Operation –Use instruction fields to select registers –Read source registers and send them to ALU –Send ALU result to destination register

Components for ALU Instrs

ALU Datapath

Memory Access Components –Register File –ALU –Data Memory –Sign-Extension Unit Operation –ALU adds base register and sign-extended immediate –Send ALU result to memory as the address –Read the value from memory into the destination register (lw) or write the value from the source register into memory (sw)

Components for Mem Access

Memory Access Datapath

Branches Components –Register File –ALU –Program Counter (PC) –Adder –Sign-Extension Unit Operation –Send source register values to ALU for comparison –Adder computes branch target address –Control logic decides whether branch is taken or not

Branch Datapath

Putting It All Together

Control Unit Control unit takes an instruction as input and produces control signals as output Types of control signals –Multiplexor selector signals –Write enables for state elements –Control signals for other blocks (ALU, etc.) In a single-cycle datapath the control unit is simple, just look up instruction in a table

Control Signals RegDst: Selects either rd or rt as the destination register RegWrite: The value on the write data port will be written into the register specified by the write register input when asserted ALUOp: Selects ALU operation ALUSrc: Selects the second ALU input to be either the second register output or the sign- extended immediate value

Control Signals (cont'd) PCSrc: Selects new PC as either PC + 4 or the output of the branch target adder –This signal is derived from the Branch control signal and the ALU's Zero output MemRead/MemWrite: Causes data memory to perform a read/write operation when asserted MemToReg: Selects either the ALU output or the data memory output as the data input into the register file

ALU Control In order to simplify design of the control unit we give the ALU its own control logic The ALU control block takes a 2-bit input from the control unit (ALUOp) and the funct field from the instruction and produces the ALU control signals

ALU Control Signals InstructionALUOpfunct FieldALU FunctionALU Inputs lw00Add0010 sw00Add0010 beq01Subtract0110 add Add0010 sub Subtract0110 and AND0000 or OR0001 slt Set on less than0111

Operation of Control Unit ALUlwswbeq ALUOp ALUSrc0110 Branch0001 MemRead0100 MemWrite0010 MemToReg01xx RegDst10xx RegWrite1100

Datapath with Control Unit

Jump Instructions The unconditional branch instruction (j) computes its branch target differently from the conditional branch instruction (beq) Branch target address is: –Top 4 bits of PC + 4 –26-bit immediate value –Two zero bits

Datapath with Jump

Performance The single-cycle datapath executes each instruction in just one cycle CPI is 1.0, which is optimal However, minimum clock cycle time is determined by slowest instruction In practice the execution time can vary considerably between instructions making a single-cycle implementation a poor choice

Using Multiple Cycles A multi-cycle datapath splits instruction execution into multiple steps, where each step take one cycle If an instruction doesn't need a step it skips it, so different instructions run for different numbers of cycles Slow instructions don't slow down the entire processor Control unit becomes more complicated Hardware can be shared between steps

Multicycle Datapath (1)

Multicycle Differences A functional unit can be used more than once in the execution of an instruction, so long as those uses occur in different steps –Instruction memory and data memory are combined into a single unit –ALU takes over for the two separate adders Additional registers are needed to save information between steps

Multicycle Registers Instruction register (IR): hold the instruction during its execution Memory data register (MDR): hold the data read from memory for one cycle A: hold source register for one cycle B: hold source register for one cycle ALUOut: hold ALU output for one cycle

Multicycle Datapath (2)

Multicycle Datapath (3)

New Control Signals ALUSrcA: selects first ALU operand to be either the PC or the A register ALUSrcB: selects second ALU operand from: B register, constant 4, sign-extended immediate, sign-extended and shifted immediate MemtoReg: selects register file write data as coming from either ALUOut or MDR IorD: selects the memory address as coming from either PC or ALUOut

New Control Signals (cont'd) IRWrite: If asserted the memory output is written to IR PCSource: Selects the new value for the PC from: ALU, ALUOut, jump target address PCWrite: If asserted the PC is written PCWriteCond: If asserted and the zero output from the ALU is 1 then the PC is written

Instruction Execution Steps Instruction fetch Instruction decode and register fetch Execution, memory address computation, or branch completion Memory access or R-type completion Memory read completion

Instruction Fetch Fetch instruction from memory –IR ← Memory[PC] Increment the PC –PC ← PC + 4

Instruction Decode Fetch operands from register file –A ← Reg[IR[25:21]] –B ← Reg[IR[20:16]] Compute branch target address –ALUOut ← PC + (sign-extend(IR[15:0]) << 2)

Execute Load/store: Compute memory address –ALUOut ← A + sign-extend(IR[15:0]) R-type: Perform operation specified by instruction –ALUOut ← A op B Branch: Compare registers and set PC if equal –if (A == B) PC ← ALUOut Jump: Set PC to jump target address –PC ← {PC[31:28], (IR[25:0] << 2)}

Memory Access Load: Read memory word into MDR –MDR ← Memory[ALUOut] Store: Write B into memory –Memory[ALUOut] ← B R-type: Write result to destination register –Reg[IR[15:11]] ← ALUOut

Memory Read Completion Load: Write result to destination register –Reg[IR[20:16]] ← MDR

Multicycle Datapath (4)

State Machine A state machine is a sequential logic device with: –Set of states –Next-state function which determines the next state from the current state and the inputs –Output function which determines the outputs from the current state and possibly the inputs In a Moore machine the output depends only on the state; in a Mealy machine the output depends on the state and the inputs

Control with a State Machine The control unit for our multicycle datapath will be a state machine The only input is the op field of the instruction; the outputs are the control signals Each step may have multiple states if control signals depend on the instruction

Fetch and Decode States

Load and Store States

R-Type States

Branch State

Jump State

Complete State Machine

Single Cycle Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.60Irwin, PSU, 2005 Executing R Format Operations  R format operations ( add, sub, slt, and, or ) l perform the (op and funct) operation on values in rs and rt l store the result back into the Register File (into location rd) Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite R-type: oprsrtrdfunctshamt 10 l The Register File is not written every cycle (e.g. sw ), so we need an explicit write control signal for the Register File

CSE431 L05 Basic MIPS Architecture.61Irwin, PSU, 2005 Executing Load and Store Operations  Load and store operations involves l compute memory address by adding the base register (read from the Register File during decode) to the 16-bit signed-extended offset field in the instruction l store value (read from the Register File during decode) written to the Data Memory l load value, read from the Data Memory, written to the Register File Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU overflow zero ALU controlRegWrite Data Memory Address Write Data Read Data Sign Extend MemWrite MemRead 1632

CSE431 L05 Basic MIPS Architecture.62Irwin, PSU, 2005 Executing Branch Operations  Branch operations involves compare the operands read from the Register File during decode for equality ( zero ALU output) l compute the branch target address by adding the updated PC to the 16-bit signed-extended offset field in the instr Instruction Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU zero ALU control Sign Extend 1632 Shift left 2 Add 4 PC Branch target address (to branch control logic)

CSE431 L05 Basic MIPS Architecture.63Irwin, PSU, 2005 Executing Jump Operations  Jump operation involves l replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits Read Address Instruction Memory Add PC 4 Shift left 2 Jump address

CSE431 L05 Basic MIPS Architecture.64Irwin, PSU, 2005 Creating a Single Datapath from the Parts  Assemble the datapath segments and add control lines and multiplexors as needed  Single cycle design – fetch, decode and execute each instructions in one clock cycle l no datapath resource can be used more than once per instruction, so some must be duplicated (e.g., separate Instruction Memory and Data Memory, several adders) l multiplexors needed at the input of shared elements with control lines to do the selection l write signals to control writing to the Register File and Data Memory  Cycle time is determined by length of the longest path

CSE431 L05 Basic MIPS Architecture.65Irwin, PSU, 2005 Fetch, R, and Memory Access Portions MemtoReg Read Address Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero ALU controlRegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 ALUSrc

CSE431 L05 Basic MIPS Architecture.66Irwin, PSU, 2005 Adding the Control  Selecting the operations to perform (ALU, Register File and Memory read/write)  Controlling the flow of data (multiplexor inputs) I-Type: oprsrt address offset R-type: oprsrtrdfunctshamt 10  Observations l op field always in bits l addr of registers to be read are always specified by the rs field (bits 25-21) and rt field (bits 20-16); for lw and sw rs is the base register l addr. of register to be written is in one of two places – in rt (bits 20-16) for lw; in rd (bits 15-11) for R-type instructions l offset for beq, lw, and sw always in bits 15-0 J-type: optarget address

CSE431 L05 Basic MIPS Architecture.67Irwin, PSU, 2005 Single Cycle Datapath with Control Unit Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.68Irwin, PSU, 2005 R-type Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.69Irwin, PSU, 2005 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.70Irwin, PSU, 2005 Load Word Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.71Irwin, PSU, 2005 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.72Irwin, PSU, 2005 Branch Instruction Data/Control Flow Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch

CSE431 L05 Basic MIPS Architecture.73Irwin, PSU, 2005 Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

CSE431 L05 Basic MIPS Architecture.74Irwin, PSU, 2005 Single Cycle Disadvantages & Advantages  Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction l especially problematic for more complex instructions like floating point multiply  May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle but  Is simple and easy to understand Clk lwswWaste Cycle 1Cycle 2

CSE431 L05 Basic MIPS Architecture.75Irwin, PSU, 2005 Multicycle Datapath Approach  Let an instruction take more than 1 clock cycle to complete l Break up instructions into steps where each step takes a cycle while trying to -balance the amount of work to be done in each step -restrict each cycle to use only one major functional unit l Not every instruction takes the same number of clock cycles  In addition to faster clock rates, multicycle allows functional units that can be used more than once per instruction as long as they are used on different clock cycles, as a result l only need one memory – but only one memory access per cycle l need only one ALU/adder – but only one ALU operation per cycle

CSE431 L05 Basic MIPS Architecture.76Irwin, PSU, 2005  At the end of a cycle l Store values needed in a later cycle by the current instruction in an internal register (not visible to the programmer). All (except IR) hold data only between a pair of adjacent clock cycles (no write control signal needed) IR – Instruction RegisterMDR – Memory Data Register A, B – regfile read data registersALUout – ALU output register Multicycle Datapath Approach, con’t Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout l Data used by subsequent instructions are stored in programmer visible registers (i.e., register file, PC, or memory)

CSE431 L05 Basic MIPS Architecture.77Irwin, PSU, 2005 The Multicycle Datapath with Control Signals Address Read Data (Instr. or Data) Memory PC Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU Write Data IR MDR A B ALUout Sign Extend Shift left 2 ALU control Shift left 2 ALUOp Control IRWrite MemtoReg MemWrite MemRead IorD PCWrite PCWriteCond RegDst RegWrite ALUSrcA ALUSrcB zero PCSource Instr[5-0] Instr[25-0] PC[31-28] Instr[15-0] Instr[31-26] 32 28

CSE431 L05 Basic MIPS Architecture.78Irwin, PSU, 2005  Multicycle datapath control signals are not determined solely by the bits in the instruction l e.g., op code bits tell what operation the ALU should be doing, but not what instruction cycle is to be done next  Must use a finite state machine (FSM) for control l a set of states (current state stored in State Register) l next state function (determined by current state and the input) l output function (determined by current state and the input) Multicycle Control Unit Combinational control logic State Reg Inst Opcode Datapath control points Next State...

CSE431 L05 Basic MIPS Architecture.79Irwin, PSU, 2005 The Five Steps of the Load Instruction  IFetch: Instruction Fetch and Update PC  Dec: Instruction Decode, Register Read, Sign Extend Offset  Exec: Execute R-type; Calculate Memory Address; Branch Comparison; Branch and Jump Completion  Mem: Memory Read; Memory Write Completion; R- type Completion (RegFile write)  WB: Memory Read Completion (RegFile write) Cycle 1Cycle 2Cycle 3Cycle 4Cycle 5 IFetchDecExecMemWB lw INSTRUCTIONS TAKE FROM CYCLES!

CSE431 L05 Basic MIPS Architecture.80Irwin, PSU, 2005 Multicycle Advantages & Disadvantages  Uses the clock cycle efficiently – the clock cycle is timed to accommodate the slowest instruction step  Multicycle implementations allow functional units to be used more than once per instruction as long as they are used on different clock cycles but  Requires additional internal state registers, more muxes, and more complicated (FSM) control Clk Cycle 1 IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 IFetchDecExecMem lwsw IFetch R-type

CSE431 L05 Basic MIPS Architecture.81Irwin, PSU, 2005 Single Cycle vs. Multiple Cycle Timing Clk Cycle 1 Multiple Cycle Implementation: IFetchDecExecMemWB Cycle 2Cycle 3Cycle 4Cycle 5Cycle 6Cycle 7Cycle 8Cycle 9Cycle 10 IFetchDecExecMem lwsw IFetch R-type Clk Single Cycle Implementation: lwsw Waste Cycle 1Cycle 2 multicycle clock slower than 1/5 th of single cycle clock due to state register overhead

CSE431 L05 Basic MIPS Architecture.82Irwin, PSU, 2005 Next Lecture and Reminders  Next lecture l MIPS pipelined datapath review -Reading assignment – PH, Chapter  Reminders l HW2 due September 27 th l Evening midterm exam scheduled -Tuesday, October 18 th, 20:15 to 22:15, Location 113 IST -You should have let me know by now if you have a conflict !!

MIPS Subset Memory access instructions –lw, sw Arithmetic and logic instructions –add, sub, and, or, slt Branch instructions –beq, j

Instruction Formats oprsrtrdshamtfunct 31:2625:2120:1615:1110:65:0 oprsrtimmed 31:2625:2120:1615:0 opaddr 31:2625:0

Fetch-Decode-Execute In order to execute an instruction we must –Fetch the instruction from memory –Determine what the instruction is (decode) –Execute it Fetch and decode are the same for all instructions Execute depends on the type of instruction

Executing Load and Store Load –Fetch operand (base address) from register –Compute effective address –Read data from memory –Write result back to register Store –Fetch operands from registers –Compute effective address –Write data to memory

Executing Arithmetic/Logic Arithmetic/logic (add, sub, and, or, slt) –Fetch operands from registers –Perform operation –Write result back to register

Executing Branch and Jump Conditional branch (beq) –Fetch operands from registers –Compare operands –If equal add displacement to PC Jump (j) –Write new value to PC

Instruction Fetch Components –Instruction Memory –Program Counter (PC) –Adder Operation –Fetch the instruction whose address is in the PC –Increment the PC by 4

Components for Instr Fetch

Instruction Fetch Datapath

ALU Instructions Components –Register File –ALU Operation –Use instruction fields to select registers –Read source registers and send them to ALU –Send ALU result to destination register

Components for ALU Instrs

ALU Datapath

Memory Access Components –Register File –ALU –Data Memory –Sign-Extension Unit Operation –ALU adds base register and sign-extended immediate –Send ALU result to memory as the address –Read the value from memory into the destination register (lw) or write the value from the source register into memory (sw)

Components for Mem Access

Memory Access Datapath

Branches Components –Register File –ALU –Program Counter (PC) –Adder –Sign-Extension Unit Operation –Send source register values to ALU for comparison –Adder computes branch target address –Control logic decides whether branch is taken or not

Branch Datapath

Putting It All Together

Control Unit Control unit takes an instruction as input and produces control signals as output Types of control signals –Multiplexor selector signals –Write enables for state elements –Control signals for other blocks (ALU, etc.) In a single-cycle datapath the control unit is simple, just look up instruction in a table

Control Signals RegDst: Selects either rd or rt as the destination register RegWrite: The value on the write data port will be written into the register specified by the write register input when asserted ALUOp: Selects ALU operation ALUSrc: Selects the second ALU input to be either the second register output or the sign- extended immediate value

Control Signals (cont'd) PCSrc: Selects new PC as either PC + 4 or the output of the branch target adder –This signal is derived from the Branch control signal and the ALU's Zero output MemRead/MemWrite: Causes data memory to perform a read/write operation when asserted MemToReg: Selects either the ALU output or the data memory output as the data input into the register file

ALU Control In order to simplify design of the control unit we give the ALU its own control logic The ALU control block takes a 2-bit input from the control unit (ALUOp) and the funct field from the instruction and produces the ALU control signals

ALU Control Signals InstructionALUOpfunct FieldALU FunctionALU Inputs lw00Add0010 sw00Add0010 beq01Subtract0110 add Add0010 sub Subtract0110 and AND0000 or OR0001 slt Set on less than0111

Operation of Control Unit ALUlwswbeq ALUOp ALUSrc0110 Branch0001 MemRead0100 MemWrite0010 MemToReg01xx RegDst10xx RegWrite1100

Datapath with Control Unit

Jump Instructions The unconditional branch instruction (j) computes its branch target differently from the conditional branch instruction (beq) Branch target address is: –Top 4 bits of PC + 4 –26-bit immediate value –Two zero bits

Datapath with Jump

Adding the Jump Operation Read Address Instr[31-0] Instruction Memory Add PC 4 Write Data Read Addr 1 Read Addr 2 Write Addr Register File Read Data 1 Read Data 2 ALU ovf zero RegWrite Data Memory Address Write Data Read Data MemWrite MemRead Sign Extend 1632 MemtoReg ALUSrc Shift left 2 Add PCSrc RegDst ALU control ALUOp Instr[5-0] Instr[15-0] Instr[25-21] Instr[20-16] Instr[15 -11] Control Unit Instr[31-26] Branch Shift left Jump 32 Instr[25-0] 26 PC+4[31-28] 28

Performance The single-cycle datapath executes each instruction in just one cycle CPI is 1.0, which is optimal However, minimum clock cycle time is determined by slowest instruction In practice the execution time can vary considerably between instructions making a single-cycle implementation a poor choice

Using Multiple Cycles A multi-cycle datapath splits instruction execution into multiple steps, where each step take one cycle If an instruction doesn't need a step it skips it, so different instructions run for different numbers of cycles Slow instructions don't slow down the entire processor Control unit becomes more complicated Hardware can be shared between steps

Multicycle Datapath (1)

Multicycle Differences A functional unit can be used more than once in the execution of an instruction, so long as those uses occur in different steps –Instruction memory and data memory are combined into a single unit –ALU takes over for the two separate adders Additional registers are needed to save information between steps

Multicycle Datapath (2)

Multicycle Datapath (3)

Multicycle Datapath (4)

Multicycle Registers Instruction register (IR): hold the instruction during its execution Memory data register (MDR): hold the data read from memory for one cycle A: hold source register for one cycle B: hold source register for one cycle ALUOut: hold ALU output for one cycle

New Control Signals ALUSrcA: selects first ALU operand to be either the PC or the A register ALUSrcB: selects second ALU operand from: B register, constant 4, sign-extended immediate, sign-extended and shifted immediate MemtoReg: selects register file write data as coming from either ALUOut or MDR IorD: selects the memory address as coming from either PC or ALUOut

New Control Signals (cont'd) IRWrite: If asserted the memory output is written to IR PCSource: Selects the new value for the PC from: ALU, ALUOut, jump target address PCWrite: If asserted the PC is written PCWriteCond: If asserted and the zero output from the ALU is 1 then the PC is written

Instruction Execution Steps Instruction fetch Instruction decode and register fetch Execution, memory address computation, or branch completion Memory access or R-type completion Memory read completion

Instruction Fetch Fetch instruction from memory –IR ← Memory[PC] Increment the PC –PC ← PC + 4

Instruction Decode Fetch operands from register file –A ← Reg[IR[25:21]] –B ← Reg[IR[20:16]] Compute branch target address –ALUOut ← PC + (sign-extend(IR[15:0]) << 2)

Execute Load/store: Compute memory address –ALUOut ← A + sign-extend(IR[15:0]) R-type: Perform operation specified by instruction –ALUOut ← A op B Branch: Compare registers and set PC if equal –if (A == B) PC ← ALUOut Jump: Set PC to jump target address –PC ← {PC[31:28], (IR[25:0] << 2)}

Memory Access Load: Read memory word into MDR –MDR ← Memory[ALUOut] Store: Write B into memory –Memory[ALUOut] ← B R-type: Write result to destination register –Reg[IR[15:11]] ← ALUOut

Memory Read Completion Load: Write result to destination register –Reg[IR[20:16]] ← MDR

State Machine A state machine is a sequential logic device with: –Set of states –Next-state function which determines the next state from the current state and the inputs –Output function which determines the outputs from the current state and possibly the inputs In a Moore machine the output depends only on the state; in a Mealy machine the output depends on the state and the inputs

Control with a State Machine The control unit for our multicycle datapath will be a state machine The only input is the op field of the instruction; the outputs are the control signals Each step may have multiple states if control signals depend on the instruction

Fetch and Decode States

Load and Store States

R-Type States

Branch State

Jump State

Complete State Machine

Exceptions An exception is an event that causes an unscheduled transfer of control Also known as interrupts and traps Typically an interrupt is caused externally while an exception or trap is caused internally Arithmetic overflow is an example of an exception; an I/O device request is an example of an interrupt

Handling Exceptions When hardware detects an exception it transfers control to a software routine called an exception handler which is typically a part of an operating system The hardware saves the value of the PC in the exception PC (EPC) register so it can return there after the exception is handled

Determining the Cause The hardware must tell the exception handler what the cause of the exception was One way to do this is store a value into a special Cause register (MIPS) Another way is to use vectored interrupts where control is transferred to a different address depending on the cause

Exceptions to Implement Undefined instruction occurs when the op field of an instruction indicates an undefined or unimplemented instruction Arithmetic overflow occurs when the ALU indicates that overflow has occurred during an R-type instruction

Adding Exceptions The EPC register saves the old PC; it is written when the EPCWrite is asserted The Cause register records the cause of the exception; it is written when CauseWrite is asserted The IntCause signal indicates the cause of the exception Control is always transferred to 0x

Changes to the Datapath

Changes to the Control Unit

Microprogramming An alternative to state machines for control is microprogramming Each instruction corresponds to a sequence of microinstructions (a microprogram) The opcode bits specify the starting address of the microprogram within the microcode ROM. A microinstruction contains values for all of the control signals plus some sequencing control bits Microprogramming makes it easier to change the control unit or to implement complex instructions

Microprogramming (cont'd)

Multicycle Performance The multicycle datapath has a much shorter clock cycle time than the single-cycle datapath However, it also has a larger CPI Is the multicycle datapath really faster? Depends on the instruction mix Can we still do better?