1 Compacting Test Vector Sets via Strategic Use of Implications Kundan Nepal Electrical Engineering Bucknell University Lewisburg, PA Nuno Alves, Jennifer Dworak, and Iris Bahar Division of Engineering Brown University Providence, RI ICCAD Section 2A: Advances in Test Efficiency - November 2,

2 Goal and Motivation Goal: Reduce the number of test vectors while maintaining the same test coverage Why important? Test time is expensive Smaller feature sizes devices  increased logic amount  increased test data volume Increased complexity of defects and process variations require more circuit testing

3 Related techniques ATPG Static and dynamic compaction techniques Design for testability Built In Self Test (BIST) Scan chains (with on-chip decompression) Test Points

4 Our previous work Use of logic implication checkers, inserted in hardware, as a means of compacting n-detect test sets “Using implications for online error detection,” in ITC08 “Detecting errors using multi- cycle invariance information,” in DATE09

5 Invariant relationships in circuits n1 n2 n3 n4 n5 n6 n7 n8 1 0 n5=1 n8= X X 0 0 X

6 Error detection with implications n5=1 & n8=1 will generate an error in checker logic n1 n2 n3 n4 n5 n6 n7 n8 ERROR n5=1 n8=0

7 Implication Violations Can Detect Errors Appropriate checker logic can detect multiple errors with a single implication. n1 n2 n3 n4 n5 n6 n7 n8 ERROR = fault n5=1 n8=0

8 Implications for Online Error Detection Our algorithm automatically identifies implications in circuits Implication selection can be constrained by hardware overhead or delay For several circuits, we can detect almost 90% of all errors that propagate to a primary output

9 Implications for test vector compaction Why are test vector sets large? Certain faults in a circuit are hard to detect A circuit with many hard to detect faults requires lots of test vectors How can implications help? Implications may make faults easier to observe, therefore pattern count can be reduced 9

10 Why Do We Want to Detect Faults Multiple Times? Faults targeted during test are not perfect models of “real world” defects. Each “real world” defect may have its own requirements for detection. However certain observation requirements overlap. By observing a site multiple times, you have multiple opportunities to meet additional requirements for detecting real defects.

To detect the OR bridge with a test for A s-a-1, B must equal 1. OR bridge: Observation could be satisfied by observation of A s-a-1 Excitation requires satisfying an additional constraint A S B F P Q A OR B bridge 0/1 A s-a-1 1 1/1 0/0 0/1 0/0 0/ /0 Defects & Faults May Not Match 11

To detect the OR bridge with a test for A s-a-1, B must equal 0. If we observe a site multiple times with different test patterns we increase our chances of fortuitously exciting whatever un-modeled defect may be present. A S B F P Q A OR B bridge 0/1 A s-a-1 1 1/1 0/0 0/1 0/0 0/ /1 Defects & Faults May Not Match 12

13 Implications generate additional fault observations Circuit rd73 (MCNC91), has 700 faults and 7 inputs We report the fault observations after all 128 vectors were simulated Number of faults that were detected circuitOnceTwice> Five rd rd73 + 1% implications rd73 + 5% implications

14 So far, We’ve introduced implications Shown that implications can make faults easier to detect Now, Can we not only use implications for on-line error detection, but also to reduce test vector size? Selecting implications for test

Algorithm Setup Goal: Find the implications that yield the largest reduction of patterns circuit ATPG Run 15-detect vectors 15

16 Calculate Implications: Using circuit simulation and SAT-based verification, discover all implications in the circuit Discover implications Creating Fault Dictionaries ATPG Run 15-detect vectors circuit Compress implications Compress Implications: Remove dominated and low quality implications Create Fault Dictionaries ( f × p matrices) For each implication, create an individual fault dictionary with the 15- detect vectors

17 Discover implications Implication Selection ATPG Run 15-detect vectors circuit Compress implications For each fault dictionary, implication selection algorithm determines which vectors may be safely deleted while keeping 15 detects Add the best performing implication to the original circuit and repeat the process Implication selection alg. Selected implications Create Fault Dictionaries ( f × p matrices)

18 Selection Algorithm: An Example 2-Detect patterns: Fault propagate at least twice Red square indicates a fault that was propagated to a primary output (PO) Fault Pattern Original Circuit

19 Selection Algorithm: An Example Circuit with implication has more propagated faults Pattern 4 is no longer required for 2-detections. With implication #1 only 4 vectors are required Fault Pattern Circuit with Implication #1 Fault Pattern Original Circuit

20 Selection Algorithm: An Example For each implication, the algorithm continues to calculate the minimum number of 2-detect vectors Fault Pattern Fault Pattern Original Circuit

21 Selection Algorithm: An Example Once we find the best implication, which gives the best 2- detect vector count reduction, we add it to the original circuit We then restart the process Fault Pattern Circuit with Implication #1 Fault Pattern Original Circuit Circuit + 1 Implication

22 Discover implications Experimental Setting ATPG Run 15-detect vectors circuit Compress implications Stuck-at fault model Benchmarks from ISCAS85 and MCNC91 ATPG tool: Mentor Graphics FastScan Synthesis Tool: Mentor Graphics Leonardo Spectrum Implication selection alg. Selected implications Create Fault Dictionaries ( f × p matrices)

23 Vector count reduction HW overheadAverage Reduction 1%8% 5%17%

24 Online error detection and pattern reduction for different HW overheads The implication checker can have a dual purpose Circuit Test Patterns % Undetected error [ITC08] Orig.10%20%10%20% C % %7.2%4.5% C %7930.0%16.9%13.7% C %2977.2%22.6%19.1% C % %14.3%13.1% b %3623.5%12.3%9.7% clip %7125.7%11.0%10.2% misex % %12.8%9.5% rd % %7.2%6.3% Z5xp %6248.1%14.5%11.5% Z9sym % %5.6%5.2%

25 Conclusions Logic implications can be used for online error detection and test Implications optimized to reduce average pattern count: 8% Reduction (1% HW) 17% Reduction (5% HW)

26 Future Work Create more sophisticated implication selection algorithms Develop algorithms that optimize implication selection for online error detection and test together Use of cross-cycle implications

27 Compacting Test Vector Sets via Strategic Use of Implications Nuno Alves (speaker) - Kundan Nepal - Jennifer Dworak - Iris Bahar -

28 Implications and delay circuit Old Delay (ns) New Delay (ns) Delay change(n s) C C C C b clip misex rd Z5xp Z9sym Circuits with added implications corresponding to 5% HW overhead TSMC 180nm Model Preserved Critical path Delay was increased an average of 2%