Fall 08, Oct 31ELEC Lecture 8 (Updated) 1 Lecture 8: Design, Simulation Synthesis and Test Tools ELEC 2200: Digital Logic Circuits Nitin Yogi

Fall 08, Oct 31ELEC Lecture 8 (Updated) 2 X-Win32  X-Win32 is used to log into UNIX session  Use Windows Auburn login and password to log into X-Win32 session.

Fall 08, Oct 31ELEC Lecture 8 (Updated) 3 Start X-Win32 from here

Fall 08, Oct 31ELEC Lecture 8 (Updated) 4 Windows Security Alert Warning If Windows Security Alert window pops up, press OK

Fall 08, Oct 31ELEC Lecture 8 (Updated) 5 You might also get this screen Double click on “Scan for Unix/Linux hosts” Click on any of the server names and click on “Select”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 6 You might also get this screen Click “OK”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 7 X-Win32 Login Screen

Fall 08, Oct 31ELEC Lecture 8 (Updated) 8 UNIX session  Setup the softwares required to run the tools for simulation, synthesis and test  At the command prompt type the following command and hit “Enter” >> user-setup Command prompt to type commands in

Fall 08, Oct 31ELEC Lecture 8 (Updated) 9 User Setup screen Click on button “Electronics Data Analysis (EDA)”

Fall 08, Oct 31ELEC Lecture 8 (Updated) Go to the bottom of the option screen 2. Click on the following software packages: eda/Modelsim/6.4 eda/ICFlow/ eda/DFT/ Click the X button on the top right

Fall 08, Oct 31ELEC Lecture 8 (Updated) 11 Click on “Save and Quit”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 12 Press “Commit Changes” The Added modules will be displayed here

Fall 08, Oct 31ELEC Lecture 8 (Updated) 13 X-Win32 reset  Exit X-Win32 and restart the X-Win32 session again as described earlier

Fall 08, Oct 31ELEC Lecture 8 (Updated) 14 UNIX environment  When you log-in into X-Win32, the current default directory is the H: of windows system  Some useful UNIX commands >> cd : change directory >> cd.. : go up one directory >> ls : list contents of directory >> pwd : display the full path of the current dir. >> mkdir : create directory

Fall 08, Oct 31ELEC Lecture 8 (Updated) 15 Setting the simulation environment  In the current default directory, create another directory for your designs by using the mkdir command. Ex. >> mkdir my_name Do not use spaces while giving names as it may create problems in UNIX This new directory can be accessed in windows in H drive  Ex. by accessing H:\my_name  Change to this new directory using the cd command Ex. >> cd my_name  In the current design directory (ex. my_name ) run the following commands: >> vlib work >> vmap work work

Fall 08, Oct 31ELEC Lecture 8 (Updated) 16 Example VHDL code library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity my_ckt is port ( A: in bit; B: in bit; S: in bit; X: out bit; Y: out bit ); end my_ckt ; architecture behav_seq of my_ckt is signal Xtmp: bit; begin p1: process (A,B,S,Xtmp) begin if (S=‘0’) then Xtmp <= A; else Xtmp <= B; end if; if ((Xtmp = ‘0’) and (S = ‘0’)) then Y <= ‘1’; else Y <= ‘0’; end if; X <= Xtmp; end process p1; end; Need to add this for compiling

Fall 08, Oct 31ELEC Lecture 8 (Updated) 17 Designing, compiling and simulating designs  Write VHDL description in any text editor (notepad, wordpad) and save the file as *.vhd  To simulate any design, you need to compile your design first. Compile your VHDL design using the command: >> vcom e.g. >> vcom my_ckt.vhd  We shall use the tool ModelSim for simulating the design To invoke ModelSim, use the following command: >> vsim e.g. >> vsim my_ckt

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Fall 08, Oct 31ELEC Lecture 8 (Updated) Click on “View > List” to select it (displayed as a tick) 2. Click on “View > Objects” to select it (displayed as a tick)

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Fall 08, Oct 31ELEC Lecture 8 (Updated) Select the input and output signals by clicking and holding the CTRL key 2. Click “Edit > Copy”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 22 Click on the list window and then click “Edit > Paste”

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Fall 08, Oct 31ELEC Lecture 8 (Updated) 24 Right click the input signal name and then click Force

Fall 08, Oct 31ELEC Lecture 8 (Updated) 25 Enter the value of the signal over here and then click OK If the signal is of type bit_vector you will assign binary values here. Ex. “010” for a signal of type bit_vector(2 downto 0)

Fall 08, Oct 31ELEC Lecture 8 (Updated) 26 To simulate, click Simulate > Run > Run 100

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Fall 08, Oct 31ELEC Lecture 8 (Updated) 29 Click on the list window then on File > Export > Tabular list

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Fall 08, Oct 31ELEC Lecture 8 (Updated) 31 Useful resource  VHDL Design and Simulation using ModelSim /ee/mgc/quickvhdl/modelsim.html /ee/mgc/quickvhdl/modelsim.html

Fall 08, Oct 31ELEC Lecture 8 (Updated) 32 Synthesis  We shall use the tool Leonardo to synthesize the behavioral description into structural level netlist  Command to invoke Leonardo is: >> leonardo

Fall 08, Oct 31ELEC Lecture 8 (Updated) 33 Click on LeonardoSpectrum Level 3 and then click OK

Fall 08, Oct 31ELEC Lecture 8 (Updated) Click on Advanced FlowTabs 2. Under the “Technology” tab, click on the ASIC plus sign

Fall 08, Oct 31ELEC Lecture 8 (Updated) 35 Click ADK then TSMC 0.18 micron (typ), then click on “Load Library”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 36 Click the “Input” tab and then the button besides “Open files”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 37 Select the required VHDL file and click “Open”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 38 Current selected designs will be displayed in this list Click on the “Read” button to read the current selected VHDL design(s) into the tool

Fall 08, Oct 31ELEC Lecture 8 (Updated) Click the type of optimization: area or delay 3. Click “Optimize” 1. Click on “Optimize” tab

Fall 08, Oct 31ELEC Lecture 8 (Updated) Click on “Report” tab 2. Click on “Report Area”

Fall 08, Oct 31ELEC Lecture 8 (Updated) Select the report being displayed 2. Select Edit > Copy to copy the report. This can then be pasted in MS Word 1. Select the report being displayed 2. Select Edit > Copy to copy the report. This can then be pasted in MS Word

Fall 08, Oct 31ELEC Lecture 8 (Updated) 42 Click on the “Report Delay” tab and then on the button “Report Delay”

Fall 08, Oct 31ELEC Lecture 8 (Updated) Select the report being displayed 2. Select Edit > Copy to copy the report. This can then be pasted in MS Word

Fall 08, Oct 31ELEC Lecture 8 (Updated) Select “Output” tab 2. Select the Verilog option in the Format menu and enter a name for the output netlist file (*.v) 3. Click “Write”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 45 Changes in design performed by Synthesis tool Leonardo  Data-type changes Integer data type in behavioral design is mapped to bit_vector data type (array of bits) in structural design  Ex. a signal A of integer data type of range -2 7 to defined in the behavioral design is mapped/changed to a data type bit_vector(0 to 7) Enumerated / User-defined data types are encoded as binary numbers  Ex. A signal of type temperature with values (high, medium, low) defined at the behavioral level may be encoded as (00, 01, 11) at the structural level

Fall 08, Oct 31ELEC Lecture 8 (Updated) 46 Preparing for simulation of netlist  The netlist saved from Leonardo is in Verilog format (and not VHDL)  You need to compile your verilog netlist to simulate it  Before you compile your verilog netlist, you need to compile all the gate designs that your netlist uses.  The gate designs are in a file named adk.vhd at the location $ADK/technology  To compile the gate designs, type the following command in your current working directory at the command prompt: >> vcom $ADK/technology/adk.vhd -work./work/

Fall 08, Oct 31ELEC Lecture 8 (Updated) 47 Simulation of netlist  You need to compile your verilog netlist in order to simulate it. Command to compile Verilog netlist: >> vlog e.g. >> vlog my_ckt.v  Simulate the design using ModelSim Command to invoke ModelSim: >> vsim e.g. >> vsim my_ckt

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Fall 08, Oct 31ELEC Lecture 8 (Updated) 49 Test generation  We shall use the tool FlexTest to generate test vectors for the netlist  Command to invoke FlexTest: >> flextest

Fall 08, Oct 31ELEC Lecture 8 (Updated) Select the output netlist file generated by Leonardo using the Browse button 2. Click on the “Browse” button to select the ATPG Library

Fall 08, Oct 31ELEC Lecture 8 (Updated) Select the file adk.atpg in the directory /opt/ADK3.1/technology/ and then click OK

Fall 08, Oct 31ELEC Lecture 8 (Updated) 52 Invoke FlexTest

Fall 08, Oct 31ELEC Lecture 8 (Updated) 53 Click on “Done With Setup”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 54 Click on “Pattern Generation”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 55 Click on “Fault Universe”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 56 Click on “Typical”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 57 Click on “Pattern Source”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 58 Click on “Typical”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 59 Click on “Test Generation”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 60 Click on “Run with Existing Settings”

Fall 08, Oct 31ELEC Lecture 8 (Updated) 61 Click on “Save Patterns”

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Fall 08, Oct 31ELEC Lecture 8 (Updated) Check “Save the Pattern Set to a File” 2. Enter a filename for the test vector file 3. Click OK

Fall 08, Oct 31ELEC Lecture 8 (Updated) 64 Opening the pattern file saved  You can open the pattern file you just saved in the windows environment using any text editor (notepad, wordpad, Word,etc.)  The pattern file you saved will be in your current working design directory e.g. H:\my_name\  Next slide shows the pattern file

Fall 08, Oct 31ELEC Lecture 8 (Updated) 65 Total no. of faults Fault Coverage Total no. of test cycles (vectors) User CPU time