Jordi Madrenas Daniel Fernández Jordi Cosp Advanced Hardware Architectures Group Department of Electronic Engineering Universitat Politècnica de Catalunya.

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Jordi Madrenas Daniel Fernández Jordi Cosp Advanced Hardware Architectures Group Department of Electronic Engineering Universitat Politècnica de Catalunya Barcelona (Spain) A Low-Voltage Current Sorting Circuit Based on 4-T Min-Max CMOS Switch ICECS 2010 December 12th – 15th 2010 Αθηνα

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS O UTLINE 1Introduction. 2Low-voltage-drop min-max switch. 3Four-input current sorting circuit. 4Simulation results. 5Conclusion.

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS I NTRODUCTION Analog / mixed-signal processing Characteristics of mixed-signal processing -Reduced precision. -Sensitivity to mismatch, temperature, noise,... +Compact. +High-speed. +Low-power consumption. +Well-adapted for sensor processing (analog form). +Current mode style: Low-voltage/low-power.

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS I NTRODUCTION Analog / mixed-signal processing Sorter application examples:  Pattern recognition.  Median filtering.  K-winner(loser)-take-all.

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS I NTRODUCTION Self-controlled 4-transistor current switch I1I1 I2I2 I MIN I MAX V1V1 V2V2 M 1A M 2A M 2B M 1B V REF It consists of two cross-coupled current mirrors

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS I NTRODUCTION Self-controlled 4-transistor current switch DC characteristic simulation Cross-point transient measurement

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS I NTRODUCTION Sorting with the 4-transistor current switch Interesting properties  Input currents are not mirrored.  Very compact and low power. Main limitations for multi-input (multi-stage) sorting  V TH voltage drop.  V REF needs to be kept equal for both outputs.

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Low-voltage-drop min-max switch Sample/Hold min-max switch I1I1 I2I2 I MIN I MAX V1V1 V2V2 M 1A M 2A M 2B M 1B V REF SAMPLE C2C2 C1C1 SAMPLE: min-max calculation. C2C2 C1C1 V DD BYPASS HOLD HOLD: Minimizes voltage drop after sampling. BYPASS: Minimizes voltage drop before sampling.

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Low-voltage-drop min-max switch CVSL latch V DD C1C1 C2C2 C1C1 BYPASS V DD HOLD C2C2 BYPASS V DD HOLD C2C2 C1C1 V DD BYPASS HOLD

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Low-voltage-drop min-max switch Sorting basic block Sizing 0.35 μm CMOSW(µm)L(µm) Switch NMOS20.6 Sample NMOS10.35 Bypass PMOS Hold NMOS Hold PMOS CVSL PMOS0.63 CVSL NMOS30.35 HOLD BYPASS SAMPLE I2I2 I1I1 I max I min HOLD1 BYPASS1 SAMPLE1 Switch Latch

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Four-input current sorting circuit I MIN I MAX I MIN I MAX I MIN I MAX

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Simulation results BYPASS2 BYPASS3 SAMPLE1 SAMPLE2SAMPLE3 HOLD1 HOLD2 H.1 H. 2 H. 3 Control signals time (µs)

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Simulation results Input currents time (µs)

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Simulation results Output currents time (µs)

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS C ONCLUSION Compact, low-voltage current-mode sorting circuit. No need to replicate input currents. Output currents exactly follow input currents (except leakage). Ranking digital value is obtained by backtracing the CVSL latches. Voltage drop of each stage ~ tens of millivolts. Sequence of digital signals. Generated using a simple Finite State Machine (FSM). Alternatively self-timed logic can be used. Correct simulation behavior for a 4-input sorter  0.35 μm CMOS  V DD = 1.2 V  Sorts in 1 μs Future implementation in 150 nm CMOS process.

LV Current Sorting Circuit Based on 4T Min-Max CMOS Switch ICECS Thank you for your attention