Incremental Placement Algorithm for Field Programmable Gate Arrays David Leong Advisor: Guy Lemieux University of British Columbia Department of Electrical.

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Presentation transcript:

Incremental Placement Algorithm for Field Programmable Gate Arrays David Leong Advisor: Guy Lemieux University of British Columbia Department of Electrical and Computer Engineering Vancouver, BC, Canada © Copyright, David Leong, 2006

2 Contributions Incremental Placement Algorithm –iPlace –Based on Placement Locality and Floor-planning –Multi-Region Algorithm Incremental Benchmark Circuits –Synthetic Benchmark Set –Physical Re-Synthesis Benchmark Set Findings –50-260x speed up for Single-Region Benchmarks –50-70x speed up for Multi-Region Benchmarks Publications: –“Un/DoPack: Re-clustering of SOC Circuits …”, ICCAD 2006 –“iPlace, Incremental Placement for FPGAs”, Submitted to FPGA 2007

3 Motivation Runtime for placement is increasing with increasing FPGA sizes –6 hours for 50,000 LUT circuit –Time == Engineering Cost System-on-Chip circuits are made of many subcomponents What if one part is modified? –Component reuse and hierarchy –Multiple regions of the circuit need incremental placement in order to support reuse –Floor-planning for each circuit Physical Re-Synthesis Flows

4 Incremental Placement Challenges Example: –C4,C5,D4,D5 is a modified sub-circuit –Can only fit <=4 CLBs in the previous location –Free space is far away! –How do we fit >4 CLBs quickly?

5 iPlace Formulation Placement Locality –Modified Sub-Circuits should be “close” to previous location –Floorplans Expanded “Virtual” Placement Grid –Literally thinking outside of the box! Efficient Shifting Algorithm –No CPU Intensive LE/CLB swapping and cost evaluation

6 iPlace Algorithm Four Steps to Incremental Placement 1.Previous Placement and Floor-planning 2.Expanded “SuperGrid” Placement 3.Compaction Re-legalization 4.Simulated Annealing Refinement

7 Previous Placement and Floor-planning

8 Expansion Phase (SuperGrid)

9 Compaction Phase

10 Compaction Phase

11 Intermediate Solution

12 Simulated Annealing Refinement Retuned VPR Simulated Annealing Algorithm –Lower Initial Temperature (44% temp) –Smaller Range Window –Lower Temperature degradation factor (Alpha) –Variable number of swaps per temperature range, 1-3x number of CLBs

13 Benchmarking Three Benchmark Sets Single Region: –Synthetic Flow Simulates a design change –Physical Re-Synthesis flow Circuit unchanged, clustering or tech-mapping changed for optimizations Multi Region: –Physical Re-Synthesis flow Scaled to select multiple regions

14 Synthetic Benchmark Set (Syn) Developed by Dave Grant Select a rectangular region on the placement grid –Replace it with a synthetic clone –Clone can be same size, smaller, or larger (double size) Selection region of 2.5%, 5%, 10% of array size Selected Area

15 Syn: Run-Time Results -MISEX3 runtimes were too fast to measure.

16 Syn: Channel Width Results

17 Syn: Critical Path Results

18 Physical Re-Synthesis Benchmark Set (PR) Un/DoPack developed by Marvin, Guy and myself Iterative Congestion Reduction Algorithm –Select congested region –Spread out LUTs by adding whitespace to each CLB Single Congestion “Region” re-synthesized by depopulation Region selected to be 2.5%, 5%, 10%, 15% of array size

19 PR: Run-Time Results

20 PR: Channel Width Results

21 PR: Critical Path Results

22 Multi-Region Physical Resynthesis Benchmark (MR) Un/DoPack flow Multiple Regions Select all regions needed to reduce CW by 10%, 20%, 30%, 40%, 50% 1/3 to 2/3 of the entire FPGA re-synthesized

23 MR: Run-Time Results

24 MR: Channel Width Results

25 MR: Critical Path Results

26 Contributions Incremental Placement Algorithm –iPlace –Based on Placement Locality and Floor-planning –Multi-Region Algorithm Incremental Benchmark Circuits –Synthetic Benchmark Set –Physical Re-Synthesis Benchmark Set Findings –50-260x speed up for Single-Region Benchmarks –50-70x speed up for Multi-Region Benchmarks Publications: –“Un/DoPack: Re-clustering of SOC Circuits …”, ICCAD 2006 –“iPlace, Incremental Placement for FPGAs”, Submitted to FPGA 2007

27 Future Works Support for Macro Blocks Support for Carry Chains More Intelligent Shifting –Still keep it simple Integration with Commercial flows –EG: QUIP

End of Presentation, Thank you!!

Questions?