Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Development of a System-On-Chip Extensible Network Processor and debugging using Identify John W. Lockwood and Chris Zuver Applied Research Laboratory : Reconfigurable Network Group

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking FPX Hardware Platform

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking FPX Hardware in WUGS-20 Switch

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking FPX Hardware in GVS-1000 Chassis

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking System-On-Chip Firewall

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Content Matching Module regex_app (given) 32 dataen_out_appl d_out_appl sof_out_appl eof_out_appl sod_out_appl tca_out_appl clk reset_l enable_l dataen_appl_in d_appl_in sof_appl_in eof_appl_in sod_appl_in tca_appl_in Matched ready_l 32 8 To extended Bits of CAM To existing MP1 circuit From Protocol Wrappers wrapper_module.vhd

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Packet matching w/ Content Addressable Memory Sample Packet: Source Address = (dotted.decimal) Destination Address = (dotted.decimal) Source Port = 4096 (decimal) Destination Port = 80 (decimal) Protocol = TCP (6) Payload = “Consolidate your loans. CALL NOW” –Payload Lists = { General SPAM (0), Save Money SPAM (1) } –Content Vector = “ ” (binary) = x”03” (hex) Src IP (hex) = 80FC0505 Dest IP (hex) = 8D8E0202 Src Port = 1000 Dest Port = 0050 Proto = All values shown In hex Con- tent =

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Sample Filter Source Address = / 16 Destination Address = / 16 Source Port = Don’t Care Destination Port = 80 Protocol = TCP (6) Payload includes general SPAM (List 0) Src IP (hex) = 80FC0505 Dest IP (hex) = 8D8E0202 Src Port = 1000 Dest Port = 0050 Proto = Src IP value = 80FC0000 Dest IP (hex) = 8D8E0000 Src Port = 0000 Dest Port = 50 Proto = 06 Src IP (hex) = FFFF0000 Dest IP (hex) = FFFF0000 Src Port = 0000 Dest Port = FFFF Proto = FF Value Mask: 1=care 0=don’t care IP Packet Con- ten t= 01 Con- ten t= 01 Con- tent= = 03 DROP the packet : It matches the filter

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Packet Classifier with FlowID CAM MASK [1] CAM VALUE [1] CAM MASK [2] CAM VALUE [2] CAM MASK [3] CAM VALUE [3] CAM MASK [N] CAM VALUE [N] Flow ID [1] 112 bits Flow ID [2] Flow ID [3] Flow ID [N] Flow ID bits Value Comparators Mask Matchers Priority Encoder Resulting Flow Identifier Flow List Source Address Destination Address 16 bits Payload Match Bits Source Port Dest. Port Protocol - - CAM Table - - Bits in IP Header

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Other Modules Implemented IPv4 CAM Filter –104 Bit header matching Fast IP Lookup (FIPL) –Longest Prefix Match –MAE-West at 10M pkts/second Packet Content Scanner –Reg. Expression Search Data Queueing –Per-flow queue in SDRAM IPv6 Tunneling Module –Tunnels IPv6 over IPv4 Statistics Module –Event counter Traffic Generator –Per-flow mixing Video Recoder –Motion JPEG Embedded Processor –KCPSM

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Use of Identify in the FPX Design Flow Identify is natural additional to the current design flow Adds two new steps –Instrument –Debug

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Two Part Solution Instrumenter –Assigns signals to monitor/trigger –Modifies existing VHDL Does not change original vhdl (create copies) –Streamlines synthesis Debugger –Communications to hardware via JTAG –Uses trigger setup –Includes waveform viewer –Creates VHDL simulation model

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Instrumenter : Step 1 –Import Synplicity Project File –File >> Import Synplicty Project ….

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Instrumenter : Step 2 –Choose Signals to Monitor –Right-click glasses symbol near signal to Sample and Trigger Sample Only Trigger Only

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Instrumenter : Step 3 –Set Options –Click Edit IICE Options

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Device Family JTAG port Builtin – Using RJ-45 Port on FPX Syn – Adds four JTAG I/O to toplevel (map rad_test) Name of Clock in VHDL Physical Resource Usage

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking BufferType Deviceram – Block RAM Logic – Flip-Flops Number of Sample (Trade-Off: Resources)

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Triggering Options Self-Explanatory

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Instrumenter : Step 4 –INSTRUMENT DESIGN –Click “Save and Instrument Current Project”

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Synthesis Open Synplicty RUN >> Run TCL Script… Locate Synplicity.tcl in syn_projectname folder

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Synthesis VHDL Files Containing Instrumented Design Synplicity Synthesis Directory (.edf file here after running Synthesis) TCL Script for Importing to Synplicity Note: New Directory created by Instrumenter in Folder where imported Synplicity Project is located

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Continue Design Flow Add.edf file to build directory Generate Bitfile like usual Load Bitfile to FPX using NCHARGE –Make sure JTAG cable is unplugged Connect JTAG Cable to FPX and PC running IDENTIFY (Parrallel JTAG) Open IDENTIFY Debugger

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER File >> Open Project –Locate the Instrumenter Project File –Should be in same directory as Synplicity Project file

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER Trigger –Locate and set Trigger Event –Right Click Signal

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER –Setup Project Options

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER Xilinx JTAG Cable

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER RUN STOP Relative Trigger Event (Trigger Beginning, Middle, End of Sample) Locate Trigger Signals Waveform

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER Waveform

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking IDENTIFY DEBUGGER RTL View

Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking References Debugging of an Internet Packet Scheduler Using the Identify Software, by Christopher K. Zuver and John W. Lockwood, The Syndicated, Volume 4, Issue 4, An Extensible, System-On-Programmable-Chip, Content- Aware Internet Firewall, by John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, and David Lim; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, pp (Paper 14B), Sep 1-3, Automated Tools to Implement and Test Internet Systems in Reconfigurable Hardware, by John W. Lockwood, Chris Neely, Chris Zuver, Dave Lim; SIGCOMM Computer Communications Review (CCR), vol 33, no 3, July 2003, pp