Assignment 7  參考 Verilog_Numbers_Displays.pdf ，並完成實驗。

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Assignment 7  參考 Verilog_Numbers_Displays.pdf ，並完成實驗。

BCD Conversion Binary to d1 d1d2 Binary to d2 SEG7_LUT 1 SEG7_LUT 2 v[3:0] v[0:3] v[3:0] d1[3:0] d2[3:0] oSEG[6:0]

參考： SEG7_LUT Module module SEG7_LUT(oSEG,iDIG); input[3:0]iDIG; output[6:0]oSEG; reg[6:0]oSEG; begin case(iDIG) 4'h1: oSEG = 7'b ;// ---t---- 4'h2: oSEG = 7'b ; // | | 4'h3: oSEG = 7'b ; // lt rt 4'h4: oSEG = 7'b ; // | | 4'h5: oSEG = 7'b ; // ---m---- 4'h6: oSEG = 7'b ; // | | 4'h7: oSEG = 7'b ; // lb rb 4'h8: oSEG = 7'b ; // | | 4'h9: oSEG = 7'b ; // ---b---- 4'ha: oSEG = 7'b ; 4'hb: oSEG = 7'b ; 4'hc: oSEG = 7'b ; 4'hd: oSEG = 7'b ; 4'he: oSEG = 7'b ; 4'hf: oSEG = 7'b ; 4'h0: oSEG = 7'b ; endcase end endmodule

注意一： Device Assignment

注意二： Pin Assignment oHEX0_D[0]LocationPIN_AE8Yes oHEX0_D[1]LocationPIN_AF9Yes oHEX0_D[2]LocationPIN_AH9Yes oHEX0_D[3]LocationPIN_AD10Yes oHEX0_D[4]LocationPIN_AF10Yes oHEX0_D[5]LocationPIN_AD11Yes oHEX0_D[6]LocationPIN_AD12Yes oHEX0_DPLocationPIN_AF12Yes oHEX1_D[0]LocationPIN_AG13Yes oHEX1_D[1]LocationPIN_AE16Yes oHEX1_D[2]LocationPIN_AF16Yes oHEX1_D[3]LocationPIN_AG16Yes oHEX1_D[4]LocationPIN_AE17Yes oHEX1_D[5]LocationPIN_AF17Yes oHEX1_D[6]LocationPIN_AD17Yes oHEX1_DPLocationPIN_AC17Yes

注意二： Pin Assignment iSW[0]LocationPIN_AA23Yes iSW[1]LocationPIN_AB26Yes iSW[2]LocationPIN_AB25Yes iSW[3]LocationPIN_AC27Yes