GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 1 GLAST Large Area Telescope: B. Estey, G. Haller, D. Marsh SLAC (650) (650) Gamma-ray Large Area Space Telescope PDU & GASU Manufacturing Readiness Review (MRR)

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 2 Contents Overview (G. Haller) –DPU & GASU Module Description –Changes since CDR –Design and Test Documentation –Engineering Module Validation Production (B. Estey) –Parts, Materials & Processes –Procurement Status –Manufacturing Facilities –Manufacturing Flow Plan –Quality Assurance Plan –Configuration Management –Manufacturing Issues/Concerns Quality Assurance (Marsh) –Quality Assurance Plan

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 3 GLAST Large Area Telescope: G. Haller SLAC (650) Gamma-ray Large Area Space Telescope PDU & GASU MRR Overview

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 4 LAT Electronics 3 Event-Processor Units (EPU) (2 + 1 spare) –Event processing CPU –LAT Communication Board –SIB Spacecraft Interface Units (SIU)* –Storage Interface Board (SIB): Spacecraft interface, control & telemetry –LAT control CPU –LAT Communication Board (LCB): LAT command and data interface 16 Tower Electronics Modules & Tower Power Supplies * Primary & Secondary Units shown in one chassis Power-Distribution Unit (PDU)* –Spacecraft interface, power –LAT power distribution –LAT health monitoring Global-Trigger/ACD-EM/Signal-Distribution Unit* TKR CAL TKR Front-End Electronics (MCM) ACD Front-End Electronics (FREE) CAL Front-End Electronics (AFEE)

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 5 PDU & GASU Mounted on LAT GASU PDU

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 6 EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking Primary and Redundant Circuits in one Enclosure –Receives Primary and Redundant 28-V from spacecraft –Each, primary and redundant PDU can select between primary and redundant spacecraft power –Filters 28V –Turns on/off 28V to 16 towers and 3 EPU’s under program control –Protects PDU and down-stream circuits from over- current and under-voltage Over-current via poly-switches Under-voltage via custom circuit in each power- on branch –Receives command/clock from GASU –Digitizes voltages/temperatures from > 150 sources Includes temperatures from radiators, GRID; used for thermal control –Reads back data to SIU via GASU –Provides PDU DAQ voltage and temperature analog data to spacecraft for monitoring Power Distribution Module (PDU)

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 7 EM PDU enclosure with primary/redundant PDU circuit cards, no coating/staking Primary and Redundant Circuits in one Enclosure –Contains two types of circuit card assemblies GASU Power Supply CCA GASU DAQ Board CCA –GASU Power Supply Receives 28-V supply voltages for –Primary and redundant DAQ board, generates 3.3V and 2.5v –ACD FREE cards »Filteringfor 28-V »3.3V regulation –GASU DAQ Board Contains 9 FPGA’s Includes Command Response Unit, Fan-out and fan-in of commanding to 16 TEMs, PDU, EPU’s, ACD Includes Global Trigger Logic Includes LAT Event-Builder Logic Includes command/control/read-back for ACD sub-system Includes power-control for ACD FREE Boards GASU

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 8 Changes since CDR PDU –Creation/modification of PDU FPGA code –Power-on circuit was modified to include under-voltage shut-off to protect MOS power-on switches –In-rush current limits to loads modified GASU –Code in 9 FPGA’s were modified/finalized and bugs fixed –ACD power-on low-frequency system clock selection added –ACD power circuits replaced with circuit to protect for over- current and updated ICD interface voltage/current requirements

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 9 Power Peer Review RFA Status RFA 1 –Request Complete part stress and derating analysis –Response The Parts Stress and Derating Analysis has been completed (see document list on a later slide) RFA 2 –Request Need to get SEU report on Maxim parts out as soon as possible. Issue is not only LET but SET effects since transients can affect the power supply outputs –Response (NASA) The SEU testing on the Maxim parts was done in February The devices exhibited no evidence of SET or SEL to the highest fluence tested. SEUs were observed but at a level orders of magnitudes lower than required.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 10 Power Peer Review RFA Status (Continued) RFA 3 –Request Need to get AR-461 filter schematic plus schematic of supply on spacecraft. Need to develop model of power and ground distribution to verifiy filter performance relative to 100 kHz noise. Damping of the entire filter network should also be verified to assure that an interactive among the many identical filters cannot occur. –Response (SLAC) The PRU Road Show exercised the Spacecraft PRU and the LAT interface and tested the performance. The results are: –(1) The interface between the Spacecraft and LAT is understood (pinouts and signal definitions). –(2) The SIU, VCHP and DAQ feeds are stable under full load. –(3) The conducted EMI is within the requirement. –(4) The Calorimeter - Tracker mini-tower performs properly with the spacecraft PRU. –(5) There were no significant transients when the LAT feed is turned off when fully powered. The test results are documented in LAT-AM

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 11 Power Peer Review RFA Status (Continued) RFA 4 –Request T0-220 Maxim regulators have their mounting tabs connected to ground. This has the potential of creating an undesirable ground path with associated noise problems. The optimum grounding solution for this particular configuration is to connect all elements to chassis and use the structure as the primary ground return (as diagrammed on the conference room whiteboard). It is strongly recommended that this approach be taken to assure proper instrument performance despite the fact that the approach is slightly unorthodox. As a second issue, it is also suggested that gold foil or indium foil be used to assure reproducible heat sink contact for the regulators. The grease or no intermediate material approaches are strongly recommended against. –Response (SLAC) 1) The grounding approach defined in the RFA is the current implementation. The grounding tabs on the Maxim regulators are mounted directly to the enclosure, and the enclosure used as the primary ground return (2) The regulators are mounted using a thermally conductive adhesive (CV Nusil). Tests on the EM hardware showed minimal temperature rise (a few degrees) across the interface.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 12 Power Peer Review RFA Status (Continued) RFA 5 –Request Maxim part screening must be carefully done to assure that the testing provides valid verification reliability. Documented methods by Maxim are for static burn-in only (diffusion based issues) and do not represent the actual operational case planned for GLAST. In that the GLAST application is actually fairly stressful AND uses the part outside of its normal operational range (for the 1.5 volt output case), it is suggested that the screening and qual test be configured to verify the 1.5 volt configuration since it is most stressful. Note that great care must be taken with the layout and instrumentation to assure that the setup does not accidentally result in part damage. –Response (NASA/SLAC) Parts were screened and qualification testing performed at GSFC.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 13 Power Peer Review RFA Status (Continued) RFA 6 –Request The 28 volt converter planned for use by Spectrum Astro, uses a step-up transformer. A quick calculation indicates that the step-up ratio is probably 1.5 or more. therefore, a failure where the control loop goes open while the bus is at 33 volts, could put as much as 50 volts on the input to the power supply regulators. Such a condition could have catastrophic consequences to the instrument such that system level redundancy could be compromised due to progagation of the failure across interfaces. Therefore, it is strongly recommended that overvoltage protection be implemented to assure protection of the hardware plus protection against failure propagation. –Response (NASA) Lambda identified a credible single point failure that could cause an overvoltage condition. Spectrum added a transorb across the output of each 28 volt feed to prevent the voltage from exceeding 38 V. A test was run at Lambda at the end of August to verify the design. The preliminary results show that the voltage never exceeded 38 V. Spectrum Astro is reviewing the test results and performing additional studies to ensure the test results are analytically consistent with the circuitry.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 14 Power Peer Review RFA Status (Continued) LAT CDR RFA #6 Response –Action Requested: What electrical derating criteria was used on the ASICs? Define and describe. –Supporting Rationale: ASICs are required to be derated by 20% per NASA SOP for ASICs. The parts would represent a higher risk to the mission if they were not derated for their application. –Response: –The electrical derating criteria for the ASICs was based on EEE-INST-002 Instructions for EEE Parts Selection, Screening, Qualification, and Derating (NASA/TP ) Section M4 Microcircuits, Plastic Encapsulated Table 4 Microcircuit Derating Requirements for PEMs. Maximum Supply Voltage for Digital PEMs use the following formula for derating: Vn.r (Vmax.r. – Vn.r.) Where Vn.r. is the nominal rated power supply voltage Vmax.r. is the maximum rated power supply voltage For the GAFE, GARC, GCFE, GCRC, GCCC, GTCC, and GLTC -- –Vn.r. is 3.3v –Vmax.r. is 4.5v –Maximum Supply Voltage is 3.9 v –The maximum power supply for the system is 3.6v; therefore, the derating requirement is met. For the GTFE and GTRC -- –Vn.r. is 2.6v –Vmax.r. is 4.5v –Maximum Supply Voltage is 3.55 v –The maximum power supply for the system is 2.86v; therefore, the derating requirement is met.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 15 ELX Peer Review RFA Status RFA 23 –Request In order to understand EMI, perform SPICE analysis of the LAT internal power distribution bus. Include models for S/C DC/DC converters, all filters, and LAT DC/DC converters. Use model to establish EMI self-compatibility, i.e. will the internal EMI sources cause problems. Look at inrush issues as well –Response We are not able to perform SPICE level simulations due to the lack of SPICE models for the converter hybrids. However no issues were found in tests performed (PRU road-show and test-bed). EMI will be tested on the qualification models.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 16 ELX Peer Review RFA Status (Continued) RFA 24 –Request For the CDR, revise the grounding scheme chart to make it more clear and accurate. –Response –Was done for CDR

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 17 GASU Documents GASU LAT-DS GASU Assembly Signed Off LAT-PS Statement of Work, GASU Assy Signed Off LAT-DS GASU Box, Machining Signed Off LAT-DS GASU Box Signed Off LAT-DS GASU Box, Test Signed Off LAT-DS GASU Lid Signed Off LAT-DS GASU Lid, Test Signed Off LAT-DS GASU Connector Plate 1 Signed Off LAT-DS GASU Connector Plate 2 Signed Off LAT-DS GASU Connector Plate 3 Signed Off LAT-DS GASU Connector Plate 4 Signed Off LAT-DS Spider, GASU Signed Off LAT-TD FPGA Theory of Operation, AEM Signed Off LAT-DS Schematic Diagram, GASU Box Assembly Signed Off LAT-TD GASU Safe to Mate Test ProcedureDraft-In Work LAT-DS Circuit Card Assembly, GASU DAQ Signed Off LAT-DS Printed Wire Board, GASU DAQ CCA Signed Off LAT-DS PWB Fab, Loading and Assembly Signed Off LAT-DS Schematic Diagram, GASU DAQ CCA Signed Off LAT-TD Bill of Materials, GASU CCA Signed Off LAT-TD Electrical Interface Continuity and Isolation Test, GASUSigned Off LAT-TD Interface Verification Test Procedure, GASU Draft-In Work LAT-TD Parts Stress Worst Case Analysis, GASU CCA Signed Off

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 18 GASU (Con’t) LAT-DS FPGA, GASU CRU Signed Off LAT-DS Program, GASU CRU FPGA Signed Off LAT-TD VHDL, GASU-CRU FPGA Signed Off LAT-DS Design Database for GASU CRU FPGA Signed Off LAT-DS FPGA, GASU AEM Signed Off LAT-DS Program, GASU AEM FPGA Signed Off LAT-TD VHDL, GASU-AEM FPGA Signed Off LAT-DS Design Database for GASU AEM FPGA Signed Off LAT-DS FPGA, GASU TAM Draft-In Work LAT-DS Program, GASU TAM FPGA Draft-In Work LAT-TD VHDL, GASU-TAM FPGA Signed Off LAT-DS Design Database for GASU TAM FPGA Draft-In Work LAT-DS FPGA, GASU Scheduler Draft-In Work LAT-DS Program, GASU Scheduler FPGA Draft-In Work LAT-TD VHDL, GASU-Scheduler FPGA Signed Off LAT-DS Design Database for GASU Scheduler FPGA Draft-In Work GASU Trigger-related FPGA’s (Scheduler, TAM, ROIA, ROIB) in test, then release (estimate: 7 days to go)

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 19 GASU (Con’t) LAT-DS FPGA, GASU ROIa Draft-In Work LAT-DS Program, GASU ROIa FPGA Draft-In Work LAT-TD VHDL, GASU-ROIa FPGA Signed Off LAT-DS Design Database for GASU ROIa FPGA Draft-In Work LAT-TD FPGA, GASU ROIb Draft-In Work LAT-DS Program, GASU ROIb FPGA Draft-In Work LAT-TD VHDL, GASU-ROIb FPGA Draft-In Work LAT-DS Design Database for GASU ROIb FPGA Draft-In Work LAT-DS FPGA, GASU EBMOUT Signed Off LAT-DS Program, GASU EBMOUT FPGA Signed Off LAT-TD VHDL, GASU-EBMOUT FPGA Signed Off LAT-DS Design Database for GASU EBMOUT FPGA Signed Off LAT-DS FPGA, GASU EBMin_A Signed Off LAT-DS Program, GASU EBMin_A FPGA Signed Off LAT-TD VHDL, GASU-EBMin_A FPGA Signed Off LAT-DS Design Database for GASU EBMin_A FPGA Signed Off LAT-DS FPGA, GASU EBMin_B Signed Off LAT-DS Program, GASU EBMin_B FPGA Signed Off LAT-TD VHDL, GASU-EBMin_B FPGA Signed Off LAT-DS Design Database for GASU EBMin_B FPGA Signed Off

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 20 GASU (Con’t) GASU Internal Harness Assemblies LAT-DS Harness Assembly, GASU-ACD-2092 Signed Off LAT-DS Harness Assembly, GASU-SC-2093 Signed Off LAT-DS Harness Assembly, GASU-PDU-2103 Signed Off LAT-DS Harness Assembly, GASU-SIU/EPU-2104 Signed Off LAT-DS Harness Assembly, GASU-TEM_EVEN/ODD Signed Off LAT-DS Support, Cable Harness, GASU Signed Off LAT-DS Support No.2, Cable Harness, GASUSigned Off LAT-PS SOW, Internal Harness, GASU, with Glenair ConnectorSigned Off LAT-PS SOW, Internal Harness, GASU, without Glenair ConnectorSigned Off

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 21 PDU Documents Power Distribution Unit LAT-DS Assembly, Power Distribution Unit Signed Off LAT-PS Statement Of Work, PDU Signed Off LAT-DS PDU Box Machining Signed Off LAT-DS PDU Box Signed Off LAT-DS PDU Box, Test Signed Off LAT-DS PDU Lid Signed Off LAT-DS PDU Lid, Test Signed Off LAT-DS Connector Plate Left Signed Off LAT-DS Connector Plate Right Signed Off LAT-DS Screw Assembly, Tube Signed Off LAT-DS Schematic Diagram, PDU Assembly Signed Off LAT-DS Circuit Card Assembly, PDU Signed Off LAT-DS Toroid Clamp - Base, PDU Signed Off LAT-DS Toroid Clamp - Top, PDU Signed Off LAT-DS Cable Management Bracket, Long Signed Off

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 22 PDU (Con’t) LAT-TD Parts Stress/ Worst Case Analysis Signed Off LAT-TD Specification, PDU Programming ICD Being revised LAT-TD VHDL, FPGA, PDU Signed Off LAT-DS FPGA, Programmed, PDU Signed Off LAT-DS Program, PDU FPGA Signed Off LAT-DS Design Database for PDU FPGA Signed Off LAT-TD Theory of Operation, PDU VHDL Draft-In Work LAT-DS Standoff Signed Off

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 23 PDU (Con’t) PDU Internal Cable Assemblies LAT-DS Cable Assembly, PDU, PRI/RDNT J1Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J2Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J3Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J5Signed Off LAT-DS Cable Assembly, PDU PRI/RDNT J6Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J7Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J8Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J9Signed Off LAT-DS Cable Assembly, PDU, PRI/RDNT J10Signed Off LAT-DS Internal Harness Subassembly, PDU CAL Baseplate TempsSigned Off LAT-DS Internal Harness Subassembly, PDU-RAD/VCHP TempsSigned Off LAT-DS Internal Harness Subassembly, PDU-ACD/GRID/RAD TempsSigned Off LAT-PS SOW, Internal Harness, PDU, with Glenair ConnectorSigned Off LAT-PS SOW, Internal Harness, PDU, without Glenair ConnectorSigned Off

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 24 GLTC3 GLTC ASIC P/O GASU CCA LAT-DS Layout, GLTC3 ASICReleased LAT-DS Schematic, GLTC3 ASICReleased LAT-TD VHDL, GLTC3 ASICReleased LAT-TD Specification, GLTC3 ASICReleased LAT-TD Test Procedure, GLTC3 ASICSigned-off LAT-TD GLTC3 ASIC T36T Wire-bonding and Packaging RequireReleased GLTC radiation and qualification –SEL and SEU ok –TID is scheduled for next week in Italy –Qualification at GSFC will start after the radiated ASICs are tested on the test-setup, so it can be shipped to GSFC. –ASICs for flight boards are being burned in and tested, full quantity required ready within 1-2 weeks.

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 25 Engineering Model Design Validation PDU & GASU –Tested on bench and on test-bed Functionality and performance validated on test-bed 16 TEM/TPS connected to EM PDU and GASU and to SIU, EPU’s and ACD FREE’s –Validated over frequency and voltage margins –GASU used in ACD G3 test-stands at GSFC –Limitations No temperature tests performed on PDU or GASU Flight boards checked for flight component foot-prints PDU: flight board loaded with some flight components and tested GASU: no board from flight lot loaded/tested yet

GLAST LAT ProjectPDU/GASU MRR, February 4, DAQ & FSWV3 26 Issue GLTC ASIC (GASU) –ESD sensitivity about 200V Aeroflex assembly controls to < 50V Trigger FPGA code (GASU) –Only recently finalized and tested on test-bed Flight FPGA’s slower –Could not burn 9 flight FPGA’s for use on non-flight board –Finite risk Omnirel fixed-voltage regulator (PDU) –Was recalled and we are waiting for replacements, promised end of February PCB’s did not pass coupon testing (PDU) –Fabricated new batch, is at GSFC for coupon testing