An update on Power Pulsing with SDHCAL Kieffer Robert IPN Lyon « CALICE collaboration meeting » May 2011, CERN

 Intro: SDHCAL  Part I: The power pulsing with HARDROCs  Part II: Beamtest under B CERN  Conclusion Outline

 Absorber: 2 cm thick iron plates sensitive cassette readout board GRPC  Each sensitive cassette contains a readout board stick to a GRPC. 50 millions  Total (barrel + end caps): 50 millions readout channels (1x1cm 2 ) 7.5 μW/channel  HARDROC power dissipation: 7.5 μW/channel (using power pulsing) =>375 W =>375 W for the whole SDHCAL very front end boards.  Detector interface cards located on border sides host FPGAs: these cards will probably need active cooling or the use of specific power pulsed ASICs to operate data transfer tasks.  Absorber: 2 cm thick iron plates sensitive cassette readout board GRPC  Each sensitive cassette contains a readout board stick to a GRPC. 50 millions  Total (barrel + end caps): 50 millions readout channels (1x1cm 2 ) 7.5 μW/channel  HARDROC power dissipation: 7.5 μW/channel (using power pulsing) =>375 W =>375 W for the whole SDHCAL very front end boards.  Detector interface cards located on border sides host FPGAs: these cards will probably need active cooling or the use of specific power pulsed ASICs to operate data transfer tasks. SDHCAL

readout board DIF (detector interface) The readout board hosting 24 chips connected through a daisy chain scheme is controled by a DIF (detector interface) This board is fixed on a 50x33 cm 2 GRPC detector. SDHCAL power pulsing test ASU The active sensitive unit: A non-magnetic metallic cassette contains this assembly. 21/05/11 DIF Redout board 1536 channels

SDHCAL power pulsing principle 21/05/11 Readout architecture common to all calorimeters and minimization of data lines & power  Daisy chain using token ring mode  Open collector, low voltage signals  Low capacitance lines Acquisition DAQIDLE MODE Chip 0 Chip 1 Acquisition DAQIDLE MODEIDLE Chip 2 Acquisition IDLE MODEIDLE Chip 3 Acquisition IDLE MODEIDLE Chip 4 Acquisition IDLE MODEIDLEDAQ 1ms (.5%).5ms (.25%) 1% duty cycle99% duty cycle 198ms (99%) 5 events3 events 0 event 1 event 0 event Chip 0Chip 1Chip 2Chip 3Chip 4 Data bus Courtesy : N.Seguin Moreau LAL

Power Pulsing in HARDROC Power Pulsing in HARDROC ALWAYS ON  Shut down bias currents and reference voltages with vdd: ALWAYS ON POWER PULSED ON/OFF  Bandgap + other ref voltages + master I : POWER PULSED ON/OFF ALWAYS ON  Shut down bias currents and reference voltages with vdd: ALWAYS ON POWER PULSED ON/OFF  Bandgap + other ref voltages + master I : POWER PULSED ON/OFF Power pulsing lines AnlogADCDigital  3 Power pulsing lines used: Anlog, ADC, Digital setting ON/OFF the related slow control shift registers  Each stage can be power pulsed (or not) by setting ON/OFF the related slow control shift registers. Power pulsing lines AnlogADCDigital  3 Power pulsing lines used: Anlog, ADC, Digital setting ON/OFF the related slow control shift registers  Each stage can be power pulsed (or not) by setting ON/OFF the related slow control shift registers. Slow control shift registers Analog power line ADC power line

Power lines sequence Power lines sequence Power analog. (DAQ) Power DAC (DAQ) Power digital (DAQ) Power digital (POD) The Power On Digital manage the LVDS buffers to provide clock signal only when needed. When the StartReadout comes from the daisy chain loop to trigger the data transfer, Power digital line is automatically switched ON by the POD. Idle READOUT 4ms/chip Abs. Max. ACQUISITION Controled by the DIF POD module

Power consomption on HARDROC Power consomption on HARDROC HR2 ON Vdd_pa5.5 mA Vdd_fsbx312.3 mA Vdd_d0,1,27.3 mA Vdd_bandgap1.2 mA Vdd_dac0.84 mA Vddd0.67 mA vddd20.4mA (=0 if 40MHz OFF) Total (noPP)29 mA Total with 0.5% PP 145 µA Pwr_on_a alone26.5mA Pwr_on_dac1.0 mA Pwr_on_d1.0 mA ALL OFF<4µA ILD Requirement:  10 µW/ch with 0.5% duty cycle  200 µA for the entire chip (64 channels) HR2 power consomption measurement:  29 mA x 3.3V ≈ 100 mW => 1.5 mW/ch  7.5 µW/ch with 0.5% duty cycle Power consomption of each digital part Anlog ADCDigital Power consomption setting up the tree power lines: Anlog, ADC, Digital

Power pulsing under testbeam conditions

Power pulsing test beam June 2010: 10 days, SPS H2, parasitic operation Beam conditions: High Rate Aim: PowerPulsing tests using B field. PowerPulsed events: 42 kEvents Non-PowerPulsed events: 74 kEvents Beam Beam 32x48 cm 2 GRPC field B field 3T Magnet A testbeam under B field I Current (Power Pulsing)

First tests with B field Power pulsing cycle Power On Period: 10ms (100 Hz) DutyCycle: 2/10 2 ms Enable Acquisition Trigger for chip readout Injecting on falling edge through a 2pC build in capacitor Scintillator Coincidence « In Spill » Signal & Veto From Acquisition DIF Trigger Power On ASU Busy Trigger

Clock period: Time selection for triggered events: Noise contamination ratio: Noise Signal+Noise 0<EvTime<1.2us 1% 400ns Data time structure no Power Pulsing Time to trigger spectra Time to external trigger in clock counts

First tests with B field Efficiency with power pulsing About 4% efficiency loss! 3T B field Remember my CALICE CASBALANCA

suspicious behaviour power pulsingfiltered out A suspicious behaviour as been pointed out in the time to trigger distribution using power pulsing! First we filtered out these events. Digging into the data to understand Noise Signal+Noise? Signal+Noise ? Time to external trigger in clock counts the classical scheme (right peak) In the HARDROC, there is a double latch procedure applied on the BCid if the reset command is set before start_acquisition command adding 3 clock count to this timing flag: this is the classical scheme (right peak). the first trigge (left peak) On each power cycle, the first trigger is recorded without these 3 clock count because the reset happen after the start_acquisition command (left peak). Digging in the DIF’s FPGA firmware we found the reason of this double peak structure! Two kind of Bcid:

First tests with B field Digging into the data to understand Some trigger have been taken by the DIF during the waking up time. Indeed, in the firmware the trigger veto was removed during all power_on period, but before the 100μs waking time there is no data in the chip to be readed out. => First these no data triggers where thought as inefficient triggers an we lose efficiency. Spatial cut in data 20 cm Cut 13 cm Cut Position X (cm) Position Y (cm) Another firmware faillure: trigger recorded while HARDOC is sleeping Only the triggers taken in the beam area are taken in account as good events for efficiency studies.

First tests with B field Efficiency using Power Pulsing 3T B field Now we can say that: No efficiency loss No efficiency loss is found runing under power pulsing.

First tests with B field Timing of power cycle in the data Trigger taken in the same power-cycle (2ms) Trigger taken in two consecutive power-cycles (10ms) One cycle without trigger (20ms) Two cycles without trigger… Up to 11 power- cycles acquiring during a spill !!! Gaussian fit sigma: ±0.84 ms Power on 2ms

First tests with B field Summary Power pulsing scheme validated in testbeam with SDHCAL prototype, and the data is now well understood. Power consumption matches our goals. Up to now: Next:  Publish a paper about these interesting results.  Go to a large scale prof of power pulsing: maybe on SDHCAL physical protoype in a second period. (SDHCAL under construction: testbeam scheduled June 2011)

Backup slides

First tests with B field Injection with power pulsing Power On T: 100ms DutyCycle 2/ ms Enable Acquisition TriggerTrigger for chip readout Charge injection on falling edge

First tests with B field Injection with power pulsing Power On T: 100ms DutyCycle 2/ ms Enable Acquisition Trigger for chip readout Injecting on falling edge through a 2pC build in capacitor Power On DIF ASU Trigger

POWER PULSING: « AWAKE TIME » PWR ON FSB0 8 µs  All decoupling capacitors removed on bias voltages  PWR ON: ILC like (1ms,199ms)  PP of the analog part:  Input signal synchronised on PWR ON  Awake time= 8 µs DAC output (Vth) Trigger 25 µs PWR ON  Power pulsing of the 10 bit-DAC:  25 µs (slew rate limited) 21/05/1122

First tests with B field Injection with power pulsing

First tests with B field Injection with power pulsing We will use this point Charge: 0.54 pC Eff: 96.4% time stability. To check time stability.

First tests with B field Injection with power pulsing quite constant Suspecting threshold stability, we injected charges with different delays from Power- ON edge. Efficiency is quite constant during the 2ms power cycle. still ongoing Work is still ongoing to understand efficiency loss recorded on beam data.

First tests with B field Preliminary tests using B field B fieldeffect on cluster shape? Is B field having an effect on cluster shape? No Power Pulsing

Preliminary tests using B field no impactefficiency B field has no impact on efficiency. No Power Pulsing

Preliminary tests using B field B fielda bit multiplicity B field increase a bit the multiplicity. No Power Pulsing