Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010.

Slides:



Advertisements
Similar presentations
Linear Time Algorithm to Find All Relocation Positions for EUV Defect Mitigation Yuelin Du, Hongbo Zhang, Qiang Ma and Martin D. F. Wong ASPDAC13.
Advertisements

Optimal Bus Sequencing for Escape Routing in Dense PCBs H.Kong, T.Yan, M.D.F.Wong and M.M.Ozdal Department of ECE, University of Illinois at U-C ICCAD.
THERMAL-AWARE BUS-DRIVEN FLOORPLANNING PO-HSUN WU & TSUNG-YI HO Department of Computer Science and Information Engineering, National Cheng Kung University.
Chapter 4 Partition I. Covering and Dominating.
Novembro 2003 Tabu search heuristic for partition coloring1/29 XXXV SBPO XXXV SBPO Natal, 4-7 de novembro de 2003 A Tabu Search Heuristic for Partition.
Exact algorithms for the minimum latency problem Exact algorithms for the minimum latency problem 吳邦一 黃正男 詹富傑 樹德科大 資工系.
Meng-Kai Hsu, Sheng Chou, Tzu-Hen Lin, and Yao-Wen Chang Electronics Engineering, National Taiwan University Routability Driven Analytical Placement for.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
Greedy Algorithms Basic idea Connection to dynamic programming Proof Techniques.
Multi-Project Reticle Floorplanning and Wafer Dicing Andrew B. Kahng 1 Ion I. Mandoiu 2 Qinke Wang 1 Xu Xu 1 Alex Zelikovsky 3 (1) CSE Department, University.
FastPlace: Efficient Analytical Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model FastPlace: Efficient Analytical Placement.
Post-Placement Voltage Island Generation for Timing-Speculative Circuits Rong Ye†, Feng Yuan†, Zelong Sun†, Wen-Ben Jone§ and Qiang Xu†‡
An ILP-based Automatic Bus Planner for Dense PCBs P. C. Wu, Q. Ma and M. D. F. Wong Department of Electrical and Computer Engineering, University of Illinois.
MCFRoute: A Detailed Router Based on Multi- Commodity Flow Method Xiaotao Jia, Yici Cai, Qiang Zhou, Gang Chen, Zhuoyuan Li, Zuowei Li.
The Min-Max Split Delivery Multi- Depot Vehicle Routing Problem with Minimum Delivery Amounts X. Wang, B. Golden, and E. Wasil INFORMS San Francisco November.
Routability-Driven Blockage-Aware Macro Placement Yi-Fang Chen, Chau-Chin Huang, Chien-Hsiung Chiou, Yao-Wen Chang, Chang-Jen Wang.
Binary Image Compression Using Efficient Partitioning into Rectangular Regions IEEE Transactions on Communications Sherif A.Mohamed and Moustafa M. Fahmy.
MAE 552 – Heuristic Optimization Lecture 6 February 6, 2002.
SMART: A Scan-based Movement- Assisted Sensor Deployment Method in Wireless Sensor Networks Jie Wu and Shuhui Yang Department of Computer Science and Engineering.
Triple Patterning Aware Detailed Placement With Constrained Pattern Assignment Haitong Tian, Yuelin Du, Hongbo Zhang, Zigang Xiao, Martin D.F. Wong.
POLAR 2.0: An Effective Routability-Driven Placer Chris Chu Tao Lin.
Constrained Pattern Assignment for Standard Cell Based Triple Patterning Lithography H. Tian, Y. Du, H. Zhang, Z. Xiao, M. D.F. Wong Department of ECE,
Carmine Cerrone, Raffaele Cerulli, Bruce Golden GO IX Sirmione, Italy July
Routing 2 Outline –Maze Routing –Line Probe Routing –Channel Routing Goal –Understand maze routing –Understand line probe routing.
Decoupling Capacitance Allocation for Power Supply Noise Suppression Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh School of Electrical & Computer Engineering.
Chip Planning 1. Introduction Chip Planning:  Deals with large modules with −known areas −fixed/changeable shapes −(possibly fixed locations for some.
1 ENTITY test is port a: in bit; end ENTITY test; DRC LVS ERC Circuit Design Functional Design and Logic Design Physical Design Physical Verification and.
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures M. Wu, H. Chen and J. Jou Department of EE, NCTU HsinChu, Taiwan ISQED 2011.
A Topology-based ECO Routing Methodology for Mask Cost Minimization Po-Hsun Wu, Shang-Ya Bai, and Tsung-Yi Ho Department of Computer Science and Information.
 Optimal Packing of High- Precision Rectangles By Eric Huang & Richard E. Korf 25 th AAAI Conference, 2011 Florida Institute of Technology CSE 5694 Robotics.
1 Chapter 8 Linear programming is used to allocate resources, plan production, schedule workers, plan investment portfolios and formulate marketing (and.
Hongbo Zhang, Yuelin Du, Martin D.F. Wong, Yunfei Deng, Pawitter Mangat Synopsys Inc., USA Dept. of ECE, Univ. of Illinois at Urbana-Champaign GlobalFoundries.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization L. Li, Y. Ma, N. Xu, Y. Wang and X. Hong WuHan.
Network Aware Resource Allocation in Distributed Clouds.
1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese.
1 Modern Floorplanning Based on Fast Simulated Annealing Tung-Chieh Chen* and Yao-Wen Chang* # Graduate Institute of Electronics Engineering* Department.
Wen-Hao Liu 1, Yih-Lang Li 1, and Kai-Yuan Chao 2 1 Department of Computer Science, National Chiao-Tung University, Hsin-Chu, Taiwan 2 Intel Architecture.
BSG-Route: A Length-Matching Router for General Topology T. Yan and M. D. F. Wong University of Illinois at Urbana-Champaign ICCAD 2008.
Bus-Driven Floorplanning Hua Xiang*, Xiaoping Tang +, Martin D. F. Wong* * Univ. Of Illinois at Urbana-Champaign + Cadence Design Systems Inc.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
The Application of The Improved Hybrid Ant Colony Algorithm in Vehicle Routing Optimization Problem International Conference on Future Computer and Communication,
B-Escape: A Simultaneous Escape Routing Algorithm Based on Boundary Routing L. Luo, T. Yan, Q. Ma, M. D.F. Wong and T. Shibuya Department of Electrical.
How Much Randomness Makes a Tool Randomized? Petr Fišer, Jan Schmidt Faculty of Information Technology Czech Technical University in Prague
Boolean Minimizer FC-Min: Coverage Finding Process Petr Fišer, Hana Kubátová Czech Technical University Department of Computer Science and Engineering.
Approximate Dynamic Programming Methods for Resource Constrained Sensor Management John W. Fisher III, Jason L. Williams and Alan S. Willsky MIT CSAIL.
Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California,
Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning Wai-Kei Mak Dept. of Computer Science and Engineering University of South Florida.
Register Placement for High- Performance Circuits M. Chiang, T. Okamoto and T. Yoshimura Waseda University, Japan DATE 2009.
Dept. of Electrical and Computer Engineering The University of Texas at Austin E-Beam Lothography Stencil Planning and Optimization wit Overlapped Characters.
1 Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang National Taiwan.
A Memetic Algorithm for VLSI Floorplanning Maolin Tang, Member, IEEE, and Xin Yao, Fellow, IEEE IEEE TRANSACTIONS ON SYSTEMS, MAN, AND CYBERNETICS—PART.
Rectlinear Block Packing Using the O-tree Representation Yingxin Pang Koen Lampaert Mindspeed Technologies Chung-Kuan Cheng University of California, San.
A Negotiated Congestion based Router for Simultaneous Escape Routing Q.Ma, T.Yan and Martin D.F. Wong Department of Electrical and Computer Engineering.
Peng Du, Wenbo Zhao, Shih-Hung Weng, Chung-Kuan Cheng, Ronald Graham CSE Dept., University of California, San Diego, CA Character Design and Stamp Algorithms.
A Stable Fixed-outline Floorplanning Method Song Chen and Takeshi Yoshimura Graduate School of IPS, Waseda University March, 2007.
An Efficient Linear Time Triple Patterning Solver Haitong Tian Hongbo Zhang Zigang Xiao Martin D.F. Wong ASP-DAC’15.
Layout Small-Angle Rotation and Shift for EUV Defect Mitigation
Yen-Ting Yu Iris Hui-Ru Jiang Yumin Zhang Charles Chiang DRC-Based Hotspot Detection Considering Edge Tolerance and Incomplete Specification ICCAD’14.
LEMAR: A Novel Length Matching Routing Algorithm for Analog and Mixed Signal Circuits H. Yao, Y. Cai and Q. Gao EDA Lab, Department of CS, Tsinghua University,
By P.-H. Lin, H. Zhang, M.D.F. Wong, and Y.-W. Chang Presented by Lin Liu, Michigan Tech Based on “Thermal-Driven Analog Placement Considering Device Matching”
Earliness and Tardiness Penalties Chapter 5 Elements of Sequencing and Scheduling by Kenneth R. Baker Byung-Hyun Ha R1.
An Exact Algorithm for Difficult Detailed Routing Problems Kolja Sulimma Wolfgang Kunz J. W.-Goethe Universität Frankfurt.
CS 721 Project Implementation of Hypergraph Edge Covering Algorithms By David Leung ( )
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
VLSI Physical Design Automation
Partial Reconfigurable Designs
Outline Introduction Network Model and Problem Formulation
Donghui Zhang, Tian Xia Northeastern University
Under a Concurrent and Hierarchical Scheme
Presentation transcript:

Configurable Multi-product Floorplanning Qiang Ma, Martin D.F. Wong, Kai-Yuan Chao ASP-DAC 2010

Outline Introduction Problem Formulation Methodology  Exact Algorithm  Greedy Heuristic Experimental Results Conclusions

Introduction Problem Formulation Methodology  Exact Algorithm  Greedy Heuristic Experimental Results Conclusions

Introduction Conventional ASIC or SoC design floorplan usually targets for one single product; and, high efforts in re-floorplan and re- convergence for different products are still required if there is no pre-design stage multi- product planning Therefore, the problem of designing floorplans at product or market planning stage that simultaneously optimizes multiple products

Introduction Traditional floorplanning problem  Given a set of rectangles, each with a range of aspect ratio  Generate a packing of all the rectangles s.t. The rectangles do not overlap The total area and wire length are minimized

Introduction Multi-product Floorplanning  Generate a floorplan of enough components (basic blocks) that is configurable for all the products  The rectangular region for each product is as small as possible

Introduction Problem Formulation Methodology  Exact Algorithm  Greedy Heuristic Experimental Results Conclusions

Notations Problem input  {b 1, b 2, …, b m } be the set of m basic blocks  {P 1, P 2, …, P q } be the set of q products  [D i 1, D i 2, …, D i m ] T be the Demand Vector D i of P i

Notations Cutline  a line obtained by extending the interval of a block boundary Valid Region  A rectangular region R on a candidate floorplan formed by four Cutlines l, r, t, b (denoted by R(l, r, t, b)) Capacity Vector  C R = [C R 1, C R 2, …, C R m ] T of a Valid Region R, where C R j denotes # of basic block b j lying within R Feasible Region  R is Feasible for product P i if and only if C R ≧ D i

Problem Formulation Multi-product Floorplanning (MPF)  Inputs: {b 1, b 2, …, b m } {P 1, P 2, …, P q } Each product P i is associated with a Demand-Vector D i  Objective: Generate a floorplan of sufficient basic blocks to accommodate all the q products The total area of the MPF for each product on the resultant floorplan is minimized

Introduction Problem Formulation Methodology  Exact Algorithm  Greedy Heuristic Experimental Results Conclusions

Preprocessing

Exact Algorithm

Horizontal Scan (H-Scan)  Determine a Horizontal Feasible Regions (HFR) for a product  Horizontal interval array H is scanned  Fix left boundary, shift right boundary until the current region contains sufficient basic blocks

Exact Algorithm Horizontal Scan (H-Scan)

Exact Algorithm Vertical Scan (V-Scan)  Given a HFR(lb, rb), find HFR*(lb, rb) with minimum height  Find positions for tb and bb s.t. (bb-tb) is minimum  At the beginning, tb = Top-Cutlines[0], bb = Bottom-Cutlines[0]  Repeat Shift bb down until R(lb, rb, tb, bb) is feasible Shift tb down until R(lb, rb, tb, bb) is infeasible Record the current height and update the best  Until bb is no longer able to be shifted downward

Exact Algorithm Vertical Scan (V-Scan)

Greedy Heuristic Given a candidate floorplan and a product P i ’s demand vector D i, the greedy heuristic behaves as follows  The feasible region R(lb, rb, tb, bb) starts with the whole floorplan  Greedily shrink the four boundaries Pick one boundary b and shift it one step towards the center Its shifting reduce R by the most  Break the tie by picking the least recently used boundary The feasibility of R is maintained Scan Horizontal interval array H and vertical interval array V Stop when R can not be shrunk any more The resultant region R is a Minimal Feasible Region

Greedy Heuristic

Introduction Problem Formulation Methodology  Exact Algorithm  Greedy Heuristic Experimental Results Conclusions

Experimental Results Exact  Use the exact algorithm Greedy  Use the greedy heuristic Hybrid  Applying the greedy heuristic at the first stage and then switching to the exact algorithm at the second stage, when the acceptance ratio drops below a certain value  Provide good tradeoff between solution quality and rum time

Experimental Results The three method are tested and compared on a set of test cases derived from industrial data

Experimental Results

Introduction Problem Formulation Methodology  Exact Algorithm  Greedy Heuristic Experimental Results Conclusions

This paper introduced the Multi-product Floorplanning problem  Simultaneously design for a family of related products  Significantly reduce overall design time and cost First work in literature addressing this problem The effectiveness of this approach is validated by promising results on a set of test cases