HOUSEKEEPING HK at Balloon-EUSO 10 th JEM-EUSO meeting from December 5 th to 10 th at RIKEN, Tokyo By G. Medina-Tanco*, A. Zamora, L. Santiago Cruz**, F. Trillaud**, and H. Silva***. *Institue of Nuclear Science, National Autonomous University of México. **Institute of Engineering, National Autonomous University of México. *** Ebizusaki Computational Astrophysics Laboratory, RIKEN. December 7 th, 2011.

Housekeeping design based on LVPS Board at EUSO-Balloon 24V 24V to 5V DDCU 24V to 12V DDCU 24V to 15V DDCU 24V to 5V DDCU

Signal Conditioning & Command drivers Auduino Mega & Protocols Power Supply Board Conceptual drawing of HK in the case which the only interfaces are PSB and CNES.

Conceptual drawing of HK for the most general scenario, in which there are interfaces with PSB, HV, CCB and CNES.

Single-board MCU Arduino Mega 2560

 The number of available analog and digital channels in Arduino Board are more than enough to meet all TM&TC requirements. But NOTE! That interfaces with HV, CCB and CNES are not fully defined.

Finally, some important comments…  The Arduino Mega 2560 option, could be delivered in early April 2012, whereas the baseline design would be completed around mid August2012.  The Arduino Mega 2560 does not use FPGA, in consequence it is very likely that could not be used as final prototype for JEM-EUSO.  Is necessary to define the subsystem requirements in order to evaluate the feasibility of Arduino Mega 2560 option for HK at EUSO-Balloon project.

Low Voltage Power Distribution System (LVPDS) at Balloon-EUSO PSB 1 st prototype 10 th JEM-EUSO meeting from December 5 th to 10 th at RIKEN, Tokyo By H. Silva***, G. Medina-Tanco*, A. Zamora, L. Santiago Cruz**, M. Casolino***, and K. Tsuno***. *Institue of Nuclear Science, National Autonomous University of México. **Institute of Engineering, National Autonomous University of México. *** Ebizusaki Computational Astrophysics Laboratory, RIKEN. December 7 th, 2011.

As a first approach of PDMLVPS  A Power Supply Board (PSB) has been developed in México.  HVPS subsystem was based on EMCO regulator. OUR PROTOTYPE PSB 5V +12V

The interaction with PDMB requires From a power board  The PDM board receives 5V and 12V from PDMLVPS.  5V is used to produce 1.5V, 3.0V and 3.3V. Meanwhile 12V is needed for EMCO circuit section.  There are 9 regulators (final version) 3V output regulator for ASIC (3) 1.5V output regulator for ASIC (3) 3.3V output regulator for FPGA 1.5V output regulator for FPGA 0-10V output regulator for HV chip  If HVPS circuit is based on a EMCO module. One EMCO per EC consumption is 0.5W (9EC→4.5W).  HV system current consumption is ~400mA.  If HVPS circuit is based on CW the power consumption from 28V (instead 12V) is 55mW per EC (9EC→495mW). However, external control consumption is missing.  FPGA consumption is 1W ~ 2W.  PDMB Total power consumption is ~4W.  Interface power connector used is 9pin D- sub. ASIC PDM board Information provided by Aera

 Is based on three MURATA isolated DC- DC converter.  5V for PDM, 12V for HV generation chips and 5V HK monitor circuits.  UEI Q12P-C  12V/1.3A  UEI Q12P-C  5V/3A  MEV1S2405SC  5V/0.2A PSB description 24V bus voltage V&I monitoring circuits 182mm X 95mm

FeatureUEI Q12P-CUEI Q12P-CMEV1S2405SCTMP-5/5-12/1-D24-C Option/Output A / Single A to B / SingleB / Triple Vin range [V] Vin nom [V] 24 Vout [V] 1255Single +5V, dual ±12 Iout [A] , ±1 Power [W] Efficiency [%] Output Ripple/Noise [mVp-p] , Output Regulation max (line / load) ±0.05% / ±0.05%±0.05% / ±0.075%1.1% / 5%±1% / ±1.5%, ±1.5% / ±8% Under voltage shutdown [V] None Output Over Voltage Protec [V] , 15 Thermal protection shutdown [°C] Start-up time Vin to Vout regulated (max) [ms] Dimensions [mm] 27.9x24.4x x6.1x x77.2x19 Isolation Input-Output [Vdc] 2000 (full magnetic and optical) 2000 (full magnetic and optical) Input Fusing Fast blow at 4A Fuse at 0.2ASlow blow at 4A EMI Class B en55022 External caps recommended Class B en55022 External caps recommended No external components required CE - PI filter Switching Freq [kHz] ±10% Reliability issue MTBF 2x10 6 [hours]MTBF 2X10 6 [hours]MTTF 7391 [khours]--- Operating Temp [°C] -40 to to 70 Weight [g] #Pin Protections (Input/Output) UVLO UV Shutdown Start-up TH Over Temp Shutd Output current limit; Output Over Volt Rev Cond Elimin UVLO UV Shutdown Start-up TH Over Temp Shutd Output current limit; Output Over Volt Rev Cond Elimin Fully encapsulated with toroidal magnetics; No electrolytic or tantalum caps Current limit continuous and Over Voltage Protection PSB Isolated DDCUs Specifications

PSB-HK TM/TC interface electrical specs 12V DC/DC MONITOR OUTPUT5V DC/DC MONITOR OUTPUT Vcc_12V [V]*Vmon12V [V]Vcc_5V [V]*Vmon5V [V] Monitored Output Voltage levels:  A DB15 connector is proposed for transmitting voltage signals * Design calculations values NOTE! Voltage levels measured on PCB TBC

PSB-HK TM/TC interface electrical specs CURRENT MONITOR 12V OUTPUTCURRENT MONITOR 5V OUTPUT Icc_12V [A]*Vmon12V [V]Icc_5V [A]*Vmon5V [V] * Design calculations values NOTE! Voltage levels measured on PCB TBC Monitored Output Current levels:  A DB15 connector is proposed for transmitting voltage signals PIN_RET_12V PIN_RET_5V RET_12V RET_5V

PSB Bread board Model (BM) tests Upper left, voltage converters. Upper right, current monitoring circuitry. Lower left, combined view. Lower right, combined tests.

PSB Bread board Model (BM) tests Setup for the HL_Cmd tests. A program is uploaded on the chip of the Arduino Mega which sends the appropriate commands. LED lighted, a command has been sent by the Arduino Mega.

PSB Bread board Model (BM) tests Tests of the entire PSB on bread- board for passive load. Picture of the active load setup.

PSB Bread board Model (BM) tests Final printed circuit and tests of the PSB with passive and active loads.

 PSB – PDM Interface power connector is based on a 9pin D-sub right angle.  The proposal is a MDM connector approved by MIL- DTL PSB-PDM interface electrical specs E L E C T R I C A L Test voltage600V AC (sea level) 150V AC (23.4km) Current rating2.5[A] Contact resistance 8[m Ω] max at 3[A] 10 [m Ω] max at 1[A] Insulation resistance 5000[M Ω] min at 500V DC Thermal VacuumPer NASA (space class only) M E C H A N I C A L Operating Temp.-55°C to 125°C SealingHumidity Mating life500 cycles minimum Vibration20g’s MIL-STD-1344 Shock50g’s MIL-STD-1344 Contact typePre-wired, solder and PCB Number of pins9 Contact functions5V  Pins 1,2,3 12V  Pins 4,5 GND  Pins 6,7,8,9 ApprovalsMIL-STD-83513

PSB-CNES TM/TC interface electrical specs HL_cmd 12V receiver electrical characteristics: Circuit type:2 Coil Latching Relay (2 Form C) Signals:12V DC_Nom Pulse Set 12V DC_Nom Pulse Reset Reference:HL_cmd1_RET1 (HK board) HL_cmd1_RET2 (HK board) Max. applied voltage [V]150% of Nom. Voltage Coil Resistance [Ω]±10%Set coil: 400 Reset coil: 400 Nominal operating power [mW] Set coil: 360 Reset coil: 360 Nominal operating current [mA] ±10% Set coil: 30 Reset coil: 30 Operate time [Set time]Max. 10ms [10ms] Release time [Reset time]Max. 5ms [10ms] Mechanical expected lifeMin (at 600 cpm) Electrical expected lifeMin. 5x105 rated load (at 60 cpm) Weight [g] ~4~4

 The PSB latching relay receives two HL_cmd from CNES.  Voltage and current monitoring circuits will provide floating signals to HK board by DB15 connector.  Analog multiplexers and ADC are used for reading voltage digital value in programmable device.  A serial line driver is foreseen in HK board for sending TM to CNES.  HK has relay turn-on capability through open drain commands and also acquisition CC (their use is TBC).  Temperature monitoring circuit could be implemented according to requirements. PSB TM/TC interface proposal PSB

Low Voltage Power Distribution System (LVPDS) at Balloon-EUSO Actual Status 10 th JEM-EUSO meeting from December 5 th to 10 th at RIKEN, Tokyo By H. Silva***, G. Medina-Tanco*, M. Casolino***, and K. Tsuno***. *Institue of Nuclear Science, National Autonomous University of México. **Institute of Engineering, National Autonomous University of México. *** Ebizusaki Computational Astrophysics Laboratory, RIKEN. December 7 th, 2011.

Functional Block Diagram of EUSO-Balloon Instrument

So far now LVPDS interacts with…  CNES: At the moment CNES (or someone) will provide an On/Off command to a Latching Relay (LR) and LVPD will replay with contact closure (CC) signal.  PDM: This structure requires power supply lines for HVPS board and PDMB internal circuitry.  DP: This structure requires power supply levels for at least three subsystems: HK, CCB and CPU. Clock (CLK), Data storage (DST) and IR camera (IR-CAM) blocks is TBC.

LVPDS Requirements -The LVPS shall supply power to PDM and DP modules. - The LVPS shall consist in two different power distribution modules, PDMLVPS and DPLVPS. -PDMLVPS and DPLVPS shall provide isolation interface between 28V bus PWP and all subsystems. - The isolation stage will comprise isolated DDCUs with efficiencies higher than 80%. -The regulation stage shall be performed directly at load (as close as possible) for best performance. -The regulation stage will comprise isolated niPOL converters with efficiencies higher than 90%. -Propagation failures inside of LVPS modules should be controlled. If any failure event occur cannot be propagated to PWP and subsystems. -The LVPS modules shall provide ON/OFF functionality in order to be controlled from OB- SIREN. -The DDCUs shall provide low input voltage protection function to avoid malfunctions at low input voltage. -The DDCUs shall provide input circuit protection function in order to protect circuit at secondary side when over current flows to input by some abnormalities. - The DDCUs shall provide output over current protection function. - Input and Output EMI filters should be consider in design LVPS modules. - The LVPS subsystem reliability is TBD. - The maximum PCB dimensions shall match with PDM size structure.

LVPDS Environmental Requirements -The LVPS elements must endure environmental variability within industrial temperature ranges (-40°C to 85°C). - The LVPS elements must withstand shock acceleration levels of at least 15 G. - The LVPS elements must endure humidity environment conditions of TBD. LVPDS TM&TC Requirements - The PDMLVPS and DPLVPS modules shall turned On/Off by two HLCMDS. - The LVPDS modules shall provide On/Off status by CC signal. -The LVPDS modules shall provide TM information about voltage and current levels to HK system. - TM & TC format information is TBD.

The interaction with CCB requires  The CCB board needs 1.2V for FPGA core, 2.5V as auxiliary voltage and 3.3V for I/O banks.  The current baseline still in 1CCB to serve 8PDM’s.  The estimated power consumption regarding operations modes is: MODE CORE FPGA AUXILIARY VOLTAGE I/O BANKSSUMA Voltage [V]Current [A] 1 Power [W]Voltage [V]Current [A] 1 Power [W]Voltage [V]Current [A] 1 Power [W]P TOT [W] Standby 2 1,20,97751,1732,50,95452,386253,30,00460, FPGA Configuration 3 1,20,86251,0352,50,5751,43753,30,74752, PDM Configuration 4 1,22,072,4842,51,730754, ,30,00460, Normal operation 5 1,22,072,4842,52,4156,03753,30,00460,  Normal operation power consumption is 8.5W.  Voltage levels absolute max ratings 1.2V  (1.32V), 2.5V  (3V) and 3.3V  (3.75V).  Voltage levels tolerance 1.2(±5%), 2.5(±5%) and 3.3(±5%). Note 1: plus 15% margin Note 2: waiting for trigger Note 3: typical values Note 4: probably a bit lower Note 5: processing trigger Information provided by Jörg

The interaction with HK requires  The HK board needs ±15V and 5V voltage levels.  ±15V is used for signal conditioning circuit (MUX, ADC, Inst Amp and HL_cmd driver).  The 5V level is used for: Op-Amp for CC (contact closure) signal. Buffer interface with PC port. Also ADC digital part.  The Arduino Mega 2560 control board power consumption is about 1.8W.  The HK board total power consumption expected is about 3W.  In principle, HK will monitor current and voltage levels from power LVPS.  HK use a High efficiency buck switching regulator to provide 5V level.

Other interactions are:  The power consumption expected from CPU module is 12W, and 12V voltage level.  The power consumption of CLK is about 1W at 5V.  The IRCAM supply line is not defined yet. In principle, there are three options: CPU USB interface. PWP. LVPS board.  Power interfaces ?.

The proposal for DPLVPS  CPU in principle could be request 12V voltage line at input with power consumption of 12W.  Meanwhile, CLK part will require 5V at the input with 1W power consumption.  Power supply for IRCAM is TBD.

Low Voltage Power Supply subsystem at B-EUSO

T H A N K Y O U