Introducing the Nexys 2 Board CS 332 – Operating Systems 12/04/2011 by Otto Castell-R.

Slides:

Advertisements

Similar presentations

UNIT 2: Data Flow description

Advertisements

©2004 Brooks/Cole FIGURES FOR CHAPTER 10 INTRODUCTION TO VHDL Click the mouse to move to the next page. Use the ESC key to exit this chapter. This chapter.

Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering.

ENEL111 Digital Electronics

OBJECTIVES Learn the history of HDL Development. Learn how the HDL module is structured. Learn the use of operators in HDL module. Learn the different.

Introduction To VHDL for Combinational Logic

Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

1 Lecture 13 VHDL 3/16/09. 2 VHDL VHDL is a hardware description language. The behavior of a digital system can be described (specified) by writing a.

2-to-1 Multiplexer: if Statement Discussion D2.1 Example 4.

Introduction to VHDL VHDL Tutorial R. E. Haskell and D. M. Hanna T1: Combinational Logic Circuits.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

FPGAs and VHDL Lecture L12.1. FPGAs and VHDL Field Programmable Gate Arrays (FPGAs) VHDL –2 x 1 MUX –4 x 1 MUX –An Adder –Binary-to-BCD Converter –A Register.

Introduction to VHDL CSCE 496/896: Embedded Systems Witawas Srisa-an.

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #12) The slides included herein were taken from the materials.

ECE 331 – Digital System Design

CS 151 Digital Systems Design Lecture 38 Programmable Logic.

CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.

L23 – Arithmetic Logic Units. Arithmetic Logic Units (ALU)  Modern ALU design  ALU is heart of datapath  Ref: text Unit 15 9/2/2012 – ECE 3561 Lect.

AND Gate: A Logic circuit whose output is logic ‘1’ if and only if all of its inputs are logic ‘1’.

Homework 2 Due 28 th May Implement This Function using 1)a 3-to-8 Line Decoder (with OR gates) 2) a 3-to-8 Line Active Low Decoder (with NAND gates)

Computer Science, Software Engineering & Robotics Workshop, FGCU, April 27-28, 2012 FPGA: Field Programmable Gate Arrays Vincent Giannone Mentor: Dr. Janusz.

1 Part I: VHDL CODING. 2 Design StructureData TypesOperators and AttributesConcurrent DesignSequential DesignSignals and VariablesState Machines A VHDL.

Designing with FPGAs ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

CS 303 Logic & Digital System Design. Logic & Digital System Design Examles of Usage –Vending Machines –Communication System –μ-Processors –Traffic controls.

System Arch 2008 (Fire Tom Wada) /10/9 Field Programmable Gate Array.

VHDL TUTORIAL Preetha Thulasiraman ECE 223 Winter 2007.

A VHDL Tutorial ENG2410. ENG241/VHDL Tutorial2 Goals Introduce the students to the following: –VHDL as Hardware description language. –How to describe.

1 Part I: SYSTEM DESIGN. 2 Packages and Components Functions and Procedures Problem (Design & Implementation) Additional System Designs.

VHDL Introduction. V- VHSIC Very High Speed Integrated Circuit H- Hardware D- Description L- Language.

ASIC 121: Practical VHDL Digital Design for FPGAs Tutorial 1 September 27, 2006.

CWRU EECS 317 EECS 317 Computer Design LECTURE 1: The VHDL Adder Instructor: Francis G. Wolff Case Western Reserve University.

Basic Overview of VHDL Matthew Murach Slides Available at:

Digital Logic. 2 Abstractions in CS (gates) Basic Gate: Inverter IO IO GNDI O Vcc Resister (limits conductivity) Truth Table.

Anurag Dwivedi. Basic Block - Gates Gates -> Flip Flops.

HARDWARE DESCRIPTION LANGUAGE (HDL). What is HDL? A type of programming language for sampling and modeling of electronic & logic circuit designs It can.

ECE 331 – Digital System Design Single-bit Adder Circuits and Adder Circuits in VHDL (Lecture #11) The slides included herein were taken from the materials.

Hardware languages "Programming"-language for modelling of (digital) hardware 1 Two main languages: VHDL (Very High Speed Integrated Circuit Hardware Description.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, February 25 CEC 220 Digital Circuit Design Slide 1 of 19.

11 EENG 1920 Introduction to VHDL. 22 Hardware Description Language A computer language used to design circuits with text-based descriptions of the circuits.

Digital Design Using VHDL and PLDs ECOM 4311 Digital System Design Chapter 1.

Apr. 3, 2000Systems Architecture I1 Introduction to VHDL (CS 570) Jeremy R. Johnson Wed. Nov. 8, 2000.

VHDL ELEC 311 Digital Logic and Circuits Dr. Ron Hayne Images Courtesy of Cengage Learning.

May 9, 2001Systems Architecture I1 Systems Architecture I (CS ) Lab 5: Introduction to VHDL Jeremy R. Johnson May 9, 2001.

CEC 220 Digital Circuit Design Introduction to VHDL Wed, Oct 14 CEC 220 Digital Circuit Design Slide 1 of 19.

Hardware Description Languages ECE 3450 M. A. Jupina, VU, 2014.

VHDL From Ch. 5 Hardware Description Languages. History 1980’s Schematics 1990’s Hardware Description Languages –Increased due to the use of Programming.

NAND, NOR, and EXOR (more primitive logical gates) CS Computer Architecture David Mayer.

Unit 7 Mixed Language Descriptions SYLLABUS Highlights of Mixed-Language Description, How to invoke One language from the Other Mixed-language Description.

An Introduction to V.H.D.L.. Need of a Compiler… main( ) { int x=10,y=20,z; z = x + y ; printf ( “ %d “, z ); getch( ) ; } What’s That ? Give me only.

Introduction to Verilog COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals.

Combinational logic circuit

Systems Architecture Lab: Introduction to VHDL

LAB #4 Xilinix ISE Foundation Tools VHDL Design Entry “A Tutorial”

Design Entry: Schematic Capture and VHDL

HDL Programming Fundamentals

Hardware Descriptive Languages these notes are taken from Mano’s book

Field Programmable Gate Array

Field Programmable Gate Array

Field Programmable Gate Array

VHDL VHSIC Hardware Description Language VHSIC

Introduction to Verilog

Hardware Descriptive Languages these notes are taken from Mano’s book

VHDL Structural Architecture

VHDL Introduction.

LOGIC Circuits.

Presentation transcript:

Introducing the Nexys 2 Board CS 332 – Operating Systems 12/04/2011 by Otto Castell-R

FPGA FPGA – Field Programmable Gate Array Integrated Circuit which can be configured by the user Integrated Circuit which can be configured by the user Configuration is done using HDL (Hardware Description Language) Configuration is done using HDL (Hardware Description Language) FPGA's can be programmed to implement any logic function FPGA's can be programmed to implement any logic function User designs the logic circuits using AND, OR and NOT Logic Gates, which the circuit board translates into universal gates (NAND, NOR) User designs the logic circuits using AND, OR and NOT Logic Gates, which the circuit board translates into universal gates (NAND, NOR)

FPGA > Nexys 2

Logic Gates A logic gate is a physical model of a Boolean function and exists as: Elementary Gate Elementary Gate Universal Gate Universal Gate

Logic Gates – Half Adder

Logic Gates – Half Adder > SHDL module half_adder (a, b : s, r) s = /a*b+a*/b ; r = a*b ; end module

Logic Gates – Half Adder > SHDL library IEEE; library UNISIM; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity half_adder is port ( a : in std_logic ; b : in std_logic ; s : out std_logic ; r : out std_logic ); end half_adder; architecture synthesis of half_adder is begin -- concurrent statements s <= ((not a) and b) or (a and (not b)) ; r <= a and b ; end synthesis;

Logic Gates – Full Adder