TOPIC : SYNTHESIS INTRODUCTION Module 4.3 : Synthesis.

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TOPIC : SYNTHESIS DESIGN FLOW Module 4.3 Verilog Synthesis.

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Presentation transcript:

TOPIC : SYNTHESIS INTRODUCTION Module 4.3 : Synthesis

14.1 What Is Logic Synthesis?  Logic synthesis is the process of converting a high- level description of the design into an optimized gate-level representation, given a standard cell library and certain design constraints.  A standard cell library can have simple cells, such as basic logic gates like and, or, and nor, or macro cells, such as adders, muxes, and special flip-flops. A standard cell library is also known as the technology library.

Before logic synthesis tool

Computer Aided logic synthesis

Advantage of Verilog synthesis  Automated logic synthesis has significantly reduced time for conversion from high-level design representation to gates.  This has allowed designers to spend more time on designing at a higher level of representation, because less time is required for converting the design to gates.

Problems in Manual synthesis  Before the days of automated logic synthesis, when designs were converted to gates manually, the design process had the following limitations:  For large designs, manual conversion was prone to human error.  A significant portion of the design cycle was dominated by the time taken to convert a high-level design into gates.  Each designer would implement design blocks differently.  Design reuse was not possible.  Timing, area, and power dissipation in library cells are fabrication technology specific.

Automated logic synthesis benefits  Automated logic synthesis tools addressed these problems as follows:  High-level design is less prone to human error.  Conversion from high-level design to gates is fast.  Logic synthesis tools optimize the design as a whole.  Logic synthesis tools allow technology-independent design.  Design reuse is possible.  Turnaround time for redesign of blocks is shorter.  High-level design is done without significant concern about design constraints.

RTL and HDL  For the purpose of logic synthesis, designs are currently written in an HDL at a register transfer level (RTL).  The term RTL is used for an HDL description style that utilizes a combination of data flow and behavioral constructs.  Logic synthesis tools take the register transfer-level HDL description and convert it to an optimized gate-level netlist. Netlist is the description of design in terms of basic gates and their interconnection.