Review for Final Exam LC3 – Controller FPGAs Multipliers Debounce Circuit Basic Operation of N and P Type FETs Logic Gates Built from FETs

Input Forming Logic Output Forming Logic Current State LC-3 Datapath F

Current State Datapath Control IFL OFL LC-3 Datapath Next State Datapath Status

Instruction Fetch 1. Copy PC contents to MAR 2. Perform memory read enaPC = 1 & ldMAR= 1 ldMAR enaPC ldPC PC 2. Perform memory read selMDR=1 & ldMDR=1 selPC Increment PC selPC = 00 & ldPC = 1 3. Copy memory output register contents to IR enaMDR = 1 & ldIR = 1 selMDR A B ALU ldIR IR ldMDR enaMDR

The Control Logic Flip Flops OFL IFL IR N Z P aluControl nzpMatch enaMARM selEAB1 selEAB2 selMAR memWE enaALU enaMDR selMDR regWE enaPC selPC ldMDR ldMAR DR SR1 SR2 ldPC ldIR Flip Flops OFL IFL IR N Z P

The Fetch Cycle PC MAR PC  PC+1, Mem[MAR]  MDR MDR  IR Fetch0 enaPC ldMAR selPC <= “00” ldPC selMDR <= ‘1’ ldMDR Fetch1 Fetch2 enaMDR ldIR

A Note on Timing In all cases: Buses are driven and muxes are selected during a state Registers and memory inputs are latched on the rising clock edge at the end of the state

Fetch 0 master loads during the last state of the previous instruction F0 master loads

PC contents are driven onto the Bus The contents of the PC are loaded into MAR Fetch 0 Fetch 1 Fetch 2 PC contents are driven onto the Bus

The contents of the PC are loaded into MAR Fetch 0 Fetch 1 Fetch 2 MAR and F1 masters load

Data is fetched from memory / PC is incremented Fetch Instruction into MDR / Increment PC Fetch 0 Fetch 1 Fetch 2 Data is fetched from memory / PC is incremented

MDR, PC and F2 masters load Fetch Instruction into MDR / Increment PC Fetch 0 Fetch 1 Fetch 2 MDR, PC and F2 masters load

MDR contents are driven onto the Bus Load the instruction into the IR Fetch 0 Fetch 1 Fetch 2 MDR contents are driven onto the Bus

Load the instruction into the IR Fetch 0 Fetch 1 Fetch 2 IR master loads

The LEA Instruction R[DR]  PC + IR[8:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LEA 1110 DR PCoffset9 selEAB1 <= ‘0’ selEAB2 <= “10” selMAR <= ‘0’ enaMARM DR <= IR[11:9] regWE LEA0 R[DR]  PC + IR[8:0] Note that the PC Offset is always a 2’s complement (signed) value to Fetch0

The LDR Instruction MAR  R[BaseR]+offset6 MDR  Mem[MAR] R[DR]  MDR SR1 <= IR[8:6] selEAB1 <= ‘1’ selEAB2 <= “01” selMAR <= ‘0’ enaMARM ldMAR LDR0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LDR 0110 DR BaseR offset6 LDR1 selMDR <= ‘1’ ldMDR MAR  R[BaseR]+offset6 MDR  Mem[MAR] R[DR]  MDR LDR2 enaMDR DR <= IR[11:9] regWE to Fetch0

The LDI Instruction MAR  PC + IR[8:0] MDR  Mem[MAR] MAR  MDR selEAB1 <= ‘0’ selEAB2 <= “10” selMAR <= ‘0’ enaMARM ldMAR LDI0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 LDI1 LDI 1010 DR PCoffset9 selMDR <= ‘1’ ldMDR LDI2 enaMDR ldMAR MAR  PC + IR[8:0] MDR  Mem[MAR] MAR  MDR R[DR]  MDR LDI3 selMDR <= ‘1’ ldMDR LDI4 enaMDR DR <= IR[11:9] regWE to Fetch0

The STR Instruction MAR  R[BaseR]+offset MDR  R[SR] Write memory SR1 <= IR[8:6] selEAB1 <= ‘1’ selEAB2 <= “01” selMAR <= ‘0’ enaMARM ldMAR STR0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 STR 0111 SR BaseR offset6 SR1 <= IR[11:9] aluControl <= PASS enaALU selMDR <= ‘0’ ldMDR STR1 MAR  R[BaseR]+offset MDR  R[SR] Write memory STR2 memWE to Fetch0

The STI Instruction MAR  PC + IR[8:0] MDR  M[MAR] MAR  MDR selEAB1 <= ‘0’ selEAB2 <= “10” selMAR <= ‘0’ enaMARM ldMAR STI0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 STI1 STI 1011 SR PCoffset9 selMDR <= ‘1’ ldMDR STI2 enaMDR ldMAR MAR  PC + IR[8:0] MDR  M[MAR] MAR  MDR MDR  R[SR] Write memory SR1 <= IR[11:9] aluControl <= PASS enaALU selMDR <= ‘0’ ldMDR STI3 STI4 memWE to Fetch0

The JSRR Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 JSRR 0100 00 BaseR 000000 JSRR0 enaPC DR <= “111”, regWE Note: Same opcode as JSR! (determined by IR bit 11) R7  PC PC  R[BaseR] SR1 <= IR[8:6] selEAB1 <= ‘1’ selEAB2 <= “00” selPC <= “01” ldPC JSRR1 to Fetch0

FPGAs

Using ROM as Combinational Logic F A C schem1 8 x 1 ROM (LUT) A B C F lut1 tt1

Mapping Larger Functions To ROMs LUT (CD) B C D f1 LUT A’f1 + Af2 f2 F LUT (B+C) B C D A Very similar to how we decomposed functions to implement with MUX blocks…

Mapping a Gate Network to LUTs

Mapping a Gate Network to 3LUTs

Mapping Same Network to 4LUTs

Programmable logic elements (LEs) FPGAs – What Are They? Programmable logic elements (LEs) Programmable wiring areas I/O Buffers I/O Buffers I/O Buffers I/O Buffers communicate between FPGA and the outside world I/O Buffers An FPGA is a Programmable Logic Device (PLD) It can be programmed to perform any function desired.

An FPGA Architecture (Island Style) Logic Elements Column Wires Row wires Each LE is configured to do a function Wire intersections are programmed to either connect or not

Programmable Interconnect Junction Column wire =1 ON Connected Row wire Unconnected =0 OFF

Example Problem Generate the N, Z, P status flags for a microprocessor D0-D5 Z D5 N P N’

Can be done with wiring only or with 1 4LUT Example Problem Generate the N, Z, P status flags for a microprocessor Z’ D0-D5 Z D5 N P N’ Can be done with wiring only or with 1 4LUT Will require 2 4LUTs Will require 1 4LUT

LUT #7: F2 = F1•D4’•D5’  Z output N 1 2 3 4 5 D0 D1 6 7 8 9 10 P D2 11 12 13 14 15 D3 D4 D5 LUT #1: F1 = D0’• D1’• D2’• D3’ LUT #7: F2 = F1•D4’•D5’  Z output LUT #8: F3 = D5  N output LUT #9: F4 = Z’ • N’  P output Z

Configuring an FPGA An FPGA contains a configuration pin Configuration bits are shifted into FPGA using this pin, one bit per cycle Configuration bits in FPGA linked into a long shift register (SIPO) Examples on following slides  conceptual Commercial devices slightly different

Configuration Storage Structure of a 3LUT b0 b1 b2 Configuration Storage Bits (Flip Flops) b3 LUT Output b4 b5 b6 It’s just an 8:1 MUX LUT inputs select which config bit is sent to LUT output Programming LUT function  setting configuration bits b7 3 LUT Inputs

How are the Configuration Bit Flip Flops Loaded? A serial-in/parallel-out (SIPO) shift register These are the configuration bits which the LUT selects from … D Q b6 1 CLK CONFIG 1 D Q b7 CONFIG CLK …

Configuring the Programmable Interconnect Column wire Configuration bit b Arranged in a SIPO shift register also Row wire

Multipliers

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 - - - - ‘0000’ 1 0 1 Shift Register 0000 1 1 0101 Multiplier Full Adder 0101

Binary Shift/Add Multiplication Load 0101 Multiplicand Result Shift Register 1 1 1 1 - - - - ‘0000’ 0 1 Shift Register 1 1 Multiplier Full Adder 0101

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 - - - ‘0000’ 0 1 Shift Register - 1 Multiplier Full Adder

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 - - - ‘0000’ 1 0 1 Shift Register 0010 - 1 0101 Multiplier Full Adder 0111

Binary Shift/Add Multiplication Load 0111 Multiplicand Result Shift Register 1 1 1 1 1 1 - - - ‘0000’ 0 1 Shift Register - 1 Multiplier Full Adder 0111

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 1 1 - - ‘0000’ 0 1 Shift Register - - Multiplier Full Adder

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 1 1 - - ‘0000’ 0 1 Shift Register 0011 - - 0000 Multiplier Full Adder 0011

Binary Shift/Add Multiplication Load 0011 Multiplicand Result Shift Register 1 1 1 1 1 1 - - ‘0000’ 0 1 Shift Register - - Multiplier Full Adder 0011

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 1 1 - ‘0000’ 0 1 Shift Register - - - Multiplier Full Adder

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 1 1 - ‘0000’ 0 1 Shift Register 0001 - - - 0000 Multiplier Full Adder 0001

Binary Shift/Add Multiplication Load 0001 Multiplicand Result Shift Register 1 1 1 1 1 1 - ‘0000’ 0 1 Shift Register - - - Multiplier Full Adder 0001

Binary Shift/Add Multiplication Multiplicand Result Shift Register 1 1 1 1 1 1 ‘0000’ 0 1 Shift Register - - - - Multiplier Full Adder

Debouncer

Draw a State Graph S0 S3 S1 S2 noisy’ clrTimer noisy’•timerDone noisy debounced noisy•timerDone’ noisy noisy•timerDone noisy’ S2 debounced clrTimer noisy

An Improved State Graph noisy’/clrTimer Looks like the FSM can be implemented with just a single FF Do you see why there is no need for a reset input? S0 noisy•timerDone’ noisy•timerDone noisy’•timerDone S1 debounced noisy’•timerDone’ As mentioned, Mealy machines often require fewer states… noisy/clrTimer

Basic Operation of N and P Type FETs N-Type FET P-Type FET S S S S G = Vcc G = Gnd D D D D S S S S G = Gnd G = Vcc D D D D

Logic Gates Built from FETs Logic Gate Implementation Using Field Effect Transistors P I O I1 I2