Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Advanced Computer Architecture Lecture 9 DMA controller design

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Direct memory access Objective: avoid the disadvantages of programmed I/O (eliminate the busy loop) Technique –CPU writes to special controller (word count and memory address) –CPU tells controller to start data transfers –CPU continues with other computing –CPU responds to interrupt from controller: ISR

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Role of DMA controller Accept initialization data from CPU Access I/O device and drive bus (master) –Input: read I/O device and write data to memory –Output: read memory data and write to I/O device Interrupt CPU when transfer complete

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA hardware view n words adr X adr X+(n-1) Memory I/O device buffer System busadr 0 adr n-1

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller architecture Counts up from zero Counts down to zero Preset counter Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr 5 key blocks

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA initialization instructions? 1.Write start address 2.Write word count (or end address) 3.Write “go” command Each write is to a specific DMA controller port address

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller initialization 1 Start address Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller initialization 2 Word count Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller initialization 3 Start Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller driving bus Must enable all tri-state drivers: D, A, and C buses D bus sources the data, memory agent sinks the data A bus contains the memory address decoded by memory agent C bus contains the memory write code

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering DMA controller driving bus Memory write Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr Memory adr Memory data

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Hard drive DMA Assumptions –Operation: Input, or read disk, or read file –HD buffer: represent with a ROM Initialization commands –Port 1: start address –Port 2: word count –Port 4: start Design contains 5 sections Project 5

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Buffer address section Objective: create an address for the HD buffer (ROM) Role: zero counter, count up

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Buffer address block?

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Data buffer section Objective: provide data for bus transfers Role: drive the data bus when enabled and addressed

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Data buffer block?

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Word count section Objective: keep track of how many data words have been transferred Role: preset to some number, then count down to zero, indicate zero condition

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Word count block?

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Memory address section Objective: provide address for bus transfer Role: accept start address, then count up, drive the address bus

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Memory address block?

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Updated block diagram Word Count Data Buffer Memory Address Buffer Address Control D A C Xcvr Port1 Port2 BAclr BAinc WCdec MAinc Zero Ben Count

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section Objective: decode the Port instructions, request bus, transfer data across the bus, coordinate the sequence of the other blocks, interrupt CPU when done Role –Contains three subsections: decoder, counters, bus I/F –Bus I/F a FSM similar to CPU model

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 1? Decode

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 2? Counters

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 3? Bus interface

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Buffer address block? Buffer Address BAclr BAinc BAdr

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Data buffer block? Data Buffer (ROM) Data Ben BAdr Assume ROM outputs are tri-state

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Word count block? Word Count Data WCload WCdec Zero

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Memory address block? Memory Address A Assume MA outputs are tri-state D MAload MAinc Ben

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 1? Decode Logic C A Port1 (MAload) Port2 (WCload) Port4 (Start) Decode

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 2? Enables Start BAclr BAinc WCdec MAinc Zero Counters One signal?

Spring EE 437 Lillevik 437s06-l9 University of Portland School of Engineering Control section block 3? Bus I/F Bgnt Breq Int Ben Ack Inta C Must drive C bus with memory write instruction Bus interface