Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 41 Lecture 4 Yield Analysis & Product Quality n Yield and manufacturing cost n Clustered defect yield formula n Yield improvement n Defect level n Test data analysis n Example: SEMATECH chip n Summary

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 42 VLSI Chip Yield n A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. n A chip with no manufacturing defect is called a good chip. n Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. n Cost of a chip: Cost of fabricating and testing a wafer Yield x Number of chip sites on the wafer

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 43 Clustered VLSI Defects Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 44 Yield Parameters n Defect density (d ) = Average number of defects per unit of chip area n Chip area (A) Clustering parameter (  ) n Negative binomial distribution of defects, p (x ) = Prob (number of defects on a chip = x )  (  +x ) (Ad /  ) x = x !  (  ) (1+Ad /  )  +x where  is the gamma function  =0, p (x ) is a delta function (max. clustering)  =, p (x ) is Poisson distr. (no clustering) 

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 45 Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad /  )  Example: Ad = 1.0,  = 0.5, Y = 0.58 Unclustered defects:  =, Y = e - Ad Example: Ad = 1.0,  =, Y = 0.37 too pessimistic !  

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 46 Defect Level or Reject Ratio n Defect level (DL) is the ratio of faulty chips among the chips that pass tests. n DL is measured as parts per million (ppm). n DL is a measure of the effectiveness of tests. n DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 47 Determination of DL n From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL. n From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 48 Modified Yield Equation n Three parameters: n Fault density, f = average number of stuck-at faults per unit chip area Fault clustering parameter,  n Stuck-at fault coverage, T n The modified yield equation: Y (T ) = (1 + TAf /  ) -  Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af /  ) - 

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 49 Defect Level Y (T ) - Y (1) DL (T ) = Y (T ) (  + TAf )  = (  + Af )  Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A,  is the fault clustering parameter. Af and  are determined by test data analysis.

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 410 Example: SEMATECH Chip n Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont n 116,000 equivalent (2-input NAND) gates n 304-pin package, 249 I/O n Clock: 40MHz, some parts 50MHz 0.45  CMOS, 3.3V, 9.4mm x 8.8mm area n Full scan, 99.79% fault coverage n Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock n Data obtained courtesy of Phil Nigh (IBM)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 411 Test Coverage from Fault Simulator Stuck-at fault coverage Vector number

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 412 Measured Chip Fallout Vector number Measured chip fallout

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 413 Model Fitting Y (T ) for Af = 2.1 and  = Measured chip fallout Y (1) = Chip fallout and computed 1-Y (T ) Stuck-at fault coverage, T Chip fallout vs. fault coverage

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 414 Computed DL Stuck-at fault coverage (%) Defect level in ppm 237,700 ppm (Y = 76.23%)

Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 415 Summary VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (  ) n Yield drops as chip area increases; low yield means high cost n Fault coverage measures the test quality n Defect level (DL) or reject ratio is a measure of chip quality n DL can be determined by an analysis of test data n For high quality: DL < 500 ppm, fault coverage ~ 99%