Parallel Data Acquisition Systems for a Compton Camera By: Kıvanç Nurdan, T. Çonka-Nurdan CAESAR / Uni-Siegen H.J. Besch, B. Freisleben, N.A. Pavel, A.H. Walenta Uni-Siegen

INTRODUCTION Physical Facts Proposed DAQ System System Considerations Coincidence timing Proposed System Parameters Proposed DAQ System Architecture Implementation Channel Processor Subsystem Backplane Event Builder Subsystem

Current Status Extendibility of the System Discussion

Compton Camera Principle

Monolithic array of 19 hexagonal SDD’s of 5mm² of each arranged in a honeycomb configuration designed and produced by MPI Semiconductor Laboratory. Integrated on-chip JFET => low noise, excellent energy resolution Reference: C. Fiorini et al., IEEE NSS 2001 and to be published at Nucl. and Medical Imaging Science, June 2002

Anger Camera: NaI(Tl) crystal of 10” diameter and of 3/8” thickness Read out via 37 x 3” hexagonal PMTs Integrated analog readout electronics

System Considerations Time coincidence Any valid Compton event should be detected in both detectors, within 1 ns time difference. It can be assumed that they appear at the same time quanta Expected Timing Properties Trigger signal occurs 10-15 ns after an event in Gamma Camera Trigger signal occurs after 0-150 ns in Silicon Drift Detector

PROPOSED SYSTEM PARAMETERS 66 Ms/sec 12bit resolution per channel 19 channels from SDD 4 channels from Gamma Detector. 19 triggers from SDD , 1 Trigger from Gamma Detector. ( self triggering) 12 bit data and 5 bit address bus for interfacing channels to coincidence unit

Architecture:

Event Reconstruction Mechanism Each channel tracks its input continuously and creates trigger with digitally programmable threshold for any reasonable ripple in the signal, finds the peak and integral of the signal in the given time window. Coincidence logic waits for a trigger from Gamma detector then for a trigger from SDD for at most total drift time of the SDD. If and only if one SDD channel creates trigger within this time, this is taken as a true coincidence

CHANNEL PROCESSOR SUBSYSTEM Conceptional design Internal digital delay Internal trigger generation and external trigger Pre trigger delay Peak detection Integration Time stamping Raw data for direct inspection event output buffer System bus interface

Analog Stage ADC Master Controller 256 sample Prog. D. Delay Trigger Unit 32 sample Prog. Pre_trg delay Peak Event Size Controller Master Controller Integral Time 256 sample output buffer

Backplane Buffer1 Ch 1 Master Cnt. Semaphore 1 Buffer N Ch N Master Cnt. Semaphore N Bus interface

Implemented PCB Selected Hardware: 65 Msamples/s 12bit ADCs from Analog Devices. AD9235 Xilinx FPGAs : SpartanIIE Differential line receivers from Analog Devices. AD8138 Voltage regulators from National Instruments Configuration eeprom: ATMEL 17002

Channel 1 ADC 1 Conf. Memory Line receiver FPGA

Results: RAW DATA PEAK INTEGRAL TIME STAMP

BUS (backplane) Clock Distribution Central-synchronous system clock Supports 44 ( +2) parallel I/O 3 Serial I/O 2 Clock lines ( may configured for differential clocking)

Event Builder Conceptional Design An event consists of; X Y E1 E2 SDD pixel Each element has a time stamp, an integral and a peak value. ~8M detector events per second bus data transfer throughput. .7M Compton events ( depending on integration time) may be reconstructed. 10K compton events are expected for the prototype system Gamma Detector Silicon Detector

Coincidence Algorithm Wait for a trigger from Gamma Detector Trigger received from Gamma Detector, If one and only one channel from Silicon detector triggers within a max drift time, this coincidence is considered as an event candidate. GOTO 3 Else GOTO 1. If within total integration and accumulation time; no other triggers received, accept this coincidence as an event, and push its data to output buffers Else purge data GOTO 1

BUS BUS MASTER DATA SRAM ABS_REG Slave controllers Time Stamps SCAT_REGS SRAM Controller Coincidence Logic Programmable System Controller PC Interface

Parallel port interface FPGA 18x1 Mbit 133MHz SSRAM

PC interface Simple parallel port interface (implemented) 8 Mbits/sec Ethernet interface ? 100 Mbits/sec IEEE 1394 interface ? 400 Mbits/sec USB 2.0 interface ? 480 Mbits/sec

Support DAQ Software

Current Status A concept has been developed for the whole Data Acquisition System of the Compton Camera. Analog Interface and digital electronics developed and tested for the Channel Processor module. Electrical characteristics for bus architecture has been finalized and Backplane Module has been fabricated . Event builder module has been electrically characterized. Bus implementation in VHDL code is ongoing. Initial PC interface over parallel port for a single Channel Processor module has been built and DAQ software has been written to transfer data to PC.

A Possible Parallel DAQ System for a Future Compton Camera

Further Discussion Deadtime of such a system ? How fast we can go ? Extensible ? How far ? Support Software ? Balance between programmable firmware and computer software ?

References & Acknowledgements Dipl. Ing. M. Adamek (SiemensVDO A.G) (general design) Dipl. Ing. Alan Rudge (CERN) (low noise electronics) High-Speed Digital Design, H. W. Johnson, M. Graham, 1993 An Innovative Distributed Termination Scheme for GTL Backplane Bus Designs, High-Performance System Design Conference 1998 Application Report SCEA022 Texas Instruments- April 2001 Application Report SLLA067 Texas Instruments- March 2000 EIA/JESD8-8, Stub Series Terminated Logic for 3.3 V (SSTL_3) EIA/JESD8-9, Stub Series Terminated Logic for 2.5 V (SSTL_2)