Digital Design – Hardware Description Languages Chapter 9 - Hardware Description Languages.

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Presentation transcript:

Digital Design – Hardware Description Languages Chapter 9 - Hardware Description Languages

2 Digital Design Hardware Description Languages Figure 9.1 Drawn circuit.

3 Digital Design Hardware Description Languages Figure 9.2 Schematics become hard to read beyond a dozen or so components -- the graphical information becomes a nuisance rather than an aid.

4 Digital Design Hardware Description Languages Figure 9.3 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language.

5 Digital Design Hardware Description Languages (VHDL) Figure 9.4 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language, (c) textual description in the VHDL language. Bolded words are reserved words in VHDL.

6 Digital Design Hardware Description Languages (VHDL) Figure 9.7 Behavioral description of an OR gate.

7 Digital Design Hardware Description Languages (VHDL) Figure 9.8 Behavioral description off DoorOpener design.

8 Digital Design Hardware Description Languages (VHDL) Figure 9.9 Behavioral description of DoorOpener testbench. library ieee; use ieee.std_logic_1164.all; entity Testbenchis end Testbench; architecture behaviorof Testbenchis component DoorOpener port ( c, h, p:in std_logic; f:out std_logic ); end component; signal c, h, p, f: std_logic; begin DoorOpener1: DoorOpenerport map(c,h,p,f); process begin -- case 0 c <= ’0’; h <= ’0’; p <= ’0’; wait for 1ns; assert (f=’0’)report “Case 0 failed”; -- case 1 c <= ’0’; h <= ’0’; p <= ’1’; wait for 1ns; assert (f=’1’)report “Case 1 failed”; -- (cases 2-6 omitted from figure) -- case 7 c <= ’1’; h <= ’1’; p <= ’1’; wait for 1ns; assert (f=’0’)report “Case 7 failed”; wait; -- process does not wake up again end process; end behavior;

9 Digital Design Hardware Description Languages (VHDL) Figure 9.10 Behavioral description of a 4-bit register.

10 Digital Design Hardware Description Languages (VHDL) Figure 9.11 Oscillator description.

11 Digital Design Hardware Description Languages (VHDL) Figure 9.12 Behavioral description of LaserTimer controller. library ieee; use ieee.std_logic_1164.all; entity LaserTimeris port ( b:instd_logic; x:out std_logic; clk, rst:in std_logic ); end LaserTimer; architecture behaviorof LaserTimeris typestatetype is (S_Off, S_On1, S_On2, S_On3); signal currentstate, nextstate: statetype; begin statereg:process(clk, rst) begin if (rst=’1’)then currentstate <= S_Off; -- initial state elsif (clk=’1’and clk’event)then currentstate <= nextstate; end if; end process; comblogic:process (currentstate, b) begin case currentstateis when S_Off => x <= ’0’; -- laser off if (b=’0’)then nextstate <= S_Off; elsif (b=’1’)then nextstate <= S_On1; end if; when S_On1 => x <= ’1’; -- laser on nextstate <= S_On2; when S_On2 => x <= ’1’; -- laser still on nextstate <= S_On3; when S_On3 => x <= ’1’; -- laser still on nextstate <= S_Off; end case; end process; end behavior;

12 Digital Design Hardware Description Languages (VHDL) Figure 9.13 Behavioral description of a full-adder.

13 Digital Design Hardware Description Languages (VHDL) Figure 9.14 Structural description of a 4-bit carry-ripple adder.

14 Digital Design Hardware Description Languages (VHDL) Figure 9.15 Structural description of 4-bit up-counter. library ieee; use ieee.std_logic_1164.all; entity UpCounteris port ( clk:instd_logic; cnt:instd_logic; C:outstd_logic_vector(3downto 0); tc:out std_logic ); end UpCounter; architecture structureof UpCounteris component Reg4 port ( I:instd_logic_vector(3downto 0); Q:outstd_logic_vector(3downto 0); clk, ld:instd_logic ); end component; component Inc4 port ( a:instd_logic_vector(3downto 0); s:outstd_logic_vector(3downto 0); ); end component; component AND4 port ( w,x,y,z:instd_logic; F:outstd_logic ); end component; signal tempC: std_logic_vector(3downto 0); signal incC: std_logic_vector(3downto 0); begin Reg4_1: Reg4port map(incC, tempC, clk, cnt); Inc4_1: Inc4port map(tempC, incC); AND4_1: AND4port map(tempC(3), tempC(2) tempC(1), tempC(0), tc); outputC:process(tempC) begin C <= tempC; end process; end structure;

15 Digital Design Hardware Description Languages (VHDL) Figure 9.16 Structural description of top-level VHDL description of laser-based distance measurer. library ieee; use ieee.std_logic_1164.all; entity LaserDistMeasureris port ( clk, rst:in std_logic; B, S:in std_logic; L:out std_logic; D:out std_logic_vector(15downto 0) ); end LaserDistMeasurer; architecture structureof LaserDistMeasureris component LDM_Controller port ( clk, rst:in std_logic; B, S:in std_logic; L:out std_logic; Dreg_clr, Dreg_ld:out std_logic; Dctr_clr, Dctr_cnt:out std_logic ); end component; component LDM_Datapath port ( clk:in std_logic; Dreg_clr, Dreg_ld:in std_logic; Dctr_clr, Dctr_cnt:in std_logic; D:out std_logic_vector(15downto 0) ); end component; signal Dreg_clr, Dreg_ld: std_logic; signalDctr_clr, Dctr_cnt: std_logic; begin LDM_Controller_1: LDM_Controller port map (clk, rst, B, S, L, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt); LDM_Datapath_1: LDM_Datapath port map(clk, Dreg_clr, Dreg_ld, Dctr_clr, Dctr_cnt, D); end structure;

16 Digital Design Hardware Description Languages (VHDL) Figure 9.17 Structural description of the laser-based distance measurer’s datapath.

17 Digital Design Hardware Description Languages (VHDL) Figure 9.18/9.19 Behavioral description of laser-based distance measurer’s controller. library ieee; use ieee.std_logic_1164.all; entity LDM_Controlleris port ( clk, rst:in std_logic; B, S:in std_logic; L:out std_logic; Dreg_clr, Dreg_ld:out std_logic; Dctr_clr, Dctr_cnt:out std_logic ); end LDM_Controller; architecture behaviorof LDM_Controlleris type statetypeis (S0, S1, S2, S3, S4, S5); signal currentstate, nextstate: statetype; begin statereg:process(clk, rst) begin if(rst=’1’)then currentstate <= S0; -- initial state elsif (clk=’1’and clk’event)then currentstate <= nextstate; end if; end process; comblogic: process (currentstate, B, S) begin L <= ’0’; Dreg_clr <= ’0’; Dreg_ld <= ’0’; Dctr_clr <= ’0’; case currentstateis whenS0 => L <= ’0’; -- turn off laser Dreg_clr <= ’1’; -- clear Dreg nextstate <= S1; when S1 => Dctr_clr <= ’1’; -- clear timer if(B=’1’)then nextstate <= S2; else nextstate <= S1; end if; when S2 => L <= ’1’; -- turn on laser Dctr_cnt <= ’1’; -- enable timer nextstate <= S3; when S3 => L <= ’0’; -- turn off laser if (S=’1’)then nextstate <= S4; else nextstate <= S3; end if; when S4 => Dctr_cnt <= ’0’; -- disable timer nextstate <= S5; when S5 => Dreg_ld <= ’1’; -- load Dreg nextstate <= S1; end case; end process; end behavior;

18 Digital Design Hardware Description Languages (Verilog) Figure 9.5 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language, (c) textual description in the Verilog language. Bolded words are reserved words in Verilog.

19 Digital Design Hardware Description Languages (SystemC) Figure 9.6 Describing a circuit using a textual language rather than a graphical drawing: (a) schematic, (b) textual description in the English language, (c) textual description in the SystemC language. Bolded words are reserved words in SystemC.