ECE 545 Project 2 Specification

Schedule of Projects (1) Project 1 RTL design for FPGAs (20 points) Due date: Tuesday, November 22, midnight (firm) Checkpoints: Monday, October 31, noon - execution unit Monday, November 7, noon - control unit Monday, November 14, noon - testbench & verification Project 2 RTL design for standard-cell ASICs (10 points) Due date: Tuesday, December 6, midnight (firm)

Schedule of Projects (2) Project 3 Behavioral modeling (15 points) Due date: Tuesday, December 20, midnight (firm)

All Projects – Honor Code Rules Using somebody’s else code and presenting it as your own is a serious Honor Code violation and may result in an F grade for the entire course. All students are expected to write and debug their codes individually. Students are encouraged to help and support each other in all problems related to the –basic understanding of the problem –operation of the CAD tools.

Optimization Criteria Maximum ratio Throughput divided by Total Circuit Area [CLB slices] Project 1 Project 2 Throughput divided by Total Circuit Area [  m 2 ]

Project 2 - Platform & tools Target devices: standard-cell ASICs Libraries: 90 nm TCBN90G TSMC library 130 nm TCB013GHP TSMC library Tools: VHDL Simulation: Aldec Active HDL or ModelSim VHDL Synthesis: Synopsys Design Compiler

Adjust your synthesizable code for Project 1 in such a way that it can be synthesized using Synopsys and TSMC libraries of standard cells. Task 1

Prepare a comprehensive testbench capable of verifying the operation of your entire circuit and run it under ModelSim. This testbench should read test vectors from a text file. All values should be stored in the hexadecimal notation. Verify the function of your circuit using this testbench. Task 2

Synthesize your code using Synopsys for at least two sets of the circuit parameters, using the following tools and libraries: 1.Synopsys with the 90 nm TCBN90G TSMC library 2.Synopsys with the 130 nm TCB013GHP TSMC library 3.Synplify Pro using the smallest device of the Xilinx Spartan 2 family capable of holding the largest of the implemented circuits. Use at least one set of parameters recommended in the specification. Analyze, compare, and discuss the obtained netlists. Task 3

For all synthesized circuits, determine maximum clock frequency maximum throughput area ratio: maximum throughput divided by area. Compare, discuss, and explain results obtained for all analyzed cases. Explain the dependence between values of parameters (such as word size in RC6, or filter range in the IIR filter) and the area and timing of your circuit. Task 4

Optimize your circuit for the maximum throughput to area ratio. Compare, discuss, and explain results before and after the optimization. Task 5

Tips & Hints (1) Each entity and each package should be placed in a different file. The name of each file should be exactly the same as the name of an entity or package it contains. Arrange entity names in the bottom-up order (the top-most entity at the end of the list) and define this list in your script using the command blocks = { entity1, entity2, …, entityN}

Tips & Hints (2) Use only one clock in your entire design. Use an identical name for the clock signal in all your entities and packages (including declarations of components). Use the same clock name in all clock-related commands of your script, such as create_clock, set_clock_transition, etc.

Avoid advanced features, such as: multiple clocks, gated clocks, multicycle paths, circular feedback loops containing only combinational logic. Although these features are supported by Synopsys, their correct use requires additional knowledge and experience that are beyond the scope of ECE 545. Tips & Hints (3)

Tips & Hints (4) Create a project directory in your main user directory. Create the following subdirectories in the project directory: db, docs, log, reports, scripts, tb, vhdl. Place all your synthesizable source files in the vhdl directory, and your testbench files in the tb directory. Place your scripts in the script directory. Define at least the following directories close to the beginning of your script: src_directory, report_directory, db_directory.

Tips & Hints (5) Do not change values of the constraint conditions specified using the following script commands: set_clock_latency 0.1 find(clock, "clk") set_clock_transition 0.01 find(clock, "clk") set_clock_uncertainty -setup 0.1 find(clock, "clk") set_clock_uncertainty -hold 0.1 find(clock, "clk") set_load 0 all_outputs() set_input_delay 1.0 -clock clk -max all_inputs() set_output_delay -max 1.0 -clock clk all_outputs() set_wire_load_model -library tcb013ghptc -name "TSMC8K_Fsg_Conservative" You can change a clock name within these commands if necessary. These constraints are required to be the same for all students.

Tips & Hints (6) Change your current directory to your log directory before you execute design_analyzer. After executing your script within design_analyzer, analyze the contents of log files generated in the directory log. These files contain the exact description of warnings and errors generated during synthesis. Please do your best to eliminate all errors and majority of warnings generated by the scripts and written to the log files.

Project Deliverables Task 1 Source codes of all synthesizable files you have developed in order to meet the project specification. Description of any changes you have had to make in these codes in order to a. get your codes synthesized using Synopsys with TSMC libraries, b. eliminate all synthesis errors and minimize the number of synthesis warnings.

Source code of the comprehensive testbench capable of verifying the operation of your entire circuit. Input files containing test vectors, and output files containing reports from simulation. Short description of the procedure you have used to generate test vectors. Project Deliverables Task 2

Analysis of differences among netlists obtained using Synopsys and Synplify Pro. The detailed descriptions of all differences (if any) between source codes synthesizable using Synplify Pro and Synopsys. Project Deliverables Task 3

The detailed timing and area results obtained for all synthesized circuits, including maximum clock frequency critical path maximum encryption/decryption throughput area ratio: maximum encryption/decryption throughput divided by area. Project delivarables Task 4 The detailed discussion of the obtained results, containing the best possible explanation of differences among results obtained for all analyzed cases.

The detailed discussion of your optimization procedure. Project delivarables Task 5 The detailed discussion of the results obtained before and after the optimization for all analyzed cases.