Lab 5 – Digital Clock Start date: Week #8 Due date: Week #9 REPORT IS DUE WEEK #9 1

RTI subsystem Very simple system Less complicated than OC because you do not need to control output pins Less complicated means less choice for interrupt rates 2

Registers RTICTL Interrupt enable, rate select RTIFLG flag 3

Hints Get as close as possible to the real time It won’t be perfect, but it will be quite close Show calculations LCD code is available on the web for lab 4 Reminder: initialize to 12:59:59 and 0 ticks We will check the clocks by starting them all together and checking them a certain time later (~10 mins) 4

Academic Misconduct Reports and demos are submitted as a group, but it is a SINGLE group effort You may talk with other groups but sharing code or reports is NOT ALLOWED Copying code/reports from previous years is also NOT ALLOWED If we find copying we are REQUIRED to report it 5