CMS HL-LHC EM Calorimeter Upgrade M. Hansen, CERN

Upgrade Requirements l Perform the full installation and commissioning in the planned LHC long shutdown 3 l Make the system compatible with the CMS phase 2 level 1 trigger latency and rate s Up to 1 MHz trigger rate s Up to 12.5 us (25 us) level 1 trigger latency l Maintain or Improve availability s E.g. by removing interdependency for controls è please see l Mechanical compatibility with mother boards and cooling bars etc. EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Further upgrade Objectives l Improve the capability to detect and remove “spike” events in particular in the real time data sent to the level 1 trigger l Decrease the volume of services on YB0 in order to make the re-cabling easier and allow for a 30 month LS3 s E.g by decreasing the LV current to the EB Front End by using DCDC converters on the sLVRB (switching LVRB…), thus using less cables EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Phase 2 ECAL Barrel FE electronics system - Design idea l Modularity s 1 channel for readout and trigger s As legacy for services (bias, LV) l Features s Trigger-less s Streaming l Requires 10 Gbps GBT s 4 fibers per legacy tower EB phase 2 electronics upgrade kick-off M. Hansen, CERN. HSSer GBT ADC?PreAmp? PD1 APD PD2 APD PbW crystal VFE card FE card PreAmp/ADC? QIE? 9.6Gbps 4.8/9.6Gbps 9,6Gbps 4.8Gbps Controls Data stream + control handshake Data stream LV regulator board, e.g 3 rad tol DCDC

External constraints l Modularity s 25 readout channels organized as 5 phi strips s APD and low voltage connectors fully defined s Suggest to keep also the VFE – FE connector and the LVRB – FE connectors as they perform well and are rated to 3GHz l Common developments s 10Gbps è Specification discussions ongoing s Versatile link+ è In development s Low voltage regulator è Radiation and magnetic field tolerant DCDC converter in production EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

LpGBT l Down-link: 2.56 Gb/s (64 –bit frame) s User bandwidth with FEC12: 1.44 Gb/s or 36 bits / 40MHz clock l Up link: Gb/s (256 –bit frame) s User bandwidth è FEC12: 8 Gb/s è FEC5: 9.13 Gb/s s Integration : Se further slides l Phase/Frequency programmable clocks s 4 independent clocks with 50ps phase resolution s Frequencies: 40 / 80 / 160 / 320 / 640 / 1280 MHz l eLinks s Serial protocol free bidirectional links EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

LpGBT l Controls: s System control: IC channel: 80 Mb/s è Two I2C masters è Programmable parallel port:16 x DIO è Environmental parameters monitoring ø10-bit ADC with 8 inputs øTemperature sensor on chip øProgrammable current source to drive an external temperature sensor s Experiment Control: EC channel: 80Mb/s è Can control e.g a GBT-SCA øGBT Slow Control Asic l Up to 16 eLink control lanes EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

LpGBT eLinks l eLinks Gb/s s Bandwidth options è Mb/s each gives 8 usable bits / LHC clock è Mb/s each gives 16 usable bits / LHC clock è Mb/s each gives 32 usable bits / LHC clock l eLinks Gb/s s Bandwidth options è Mb/s each gives 8 usable bits / LHC clock è Mb/s each gives 16 usable bits / LHC clock è Mb/s each gives 32 usable bits / LHC clock l 3 lpGBT links provide sufficient bandwidth for the expected FE system in either FEC5 or FEC12 mode EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

FE clock distribution l Option 1a s Use the (non-skewable) eLink clocks as the only clock in the ADC / QIE (sampling, internally multiplied for eLink transmission) s Implement a PLL with clock skew function in each ADC in order to align sampling to beam è Requires a control interface, e.g. i2c l Option 1b s As option 1a but using the skewable clocks and a DLL in each ADC in order to fine tune the sampling phase è Would use the dll in “short” setting in order to preserve sampling clock quality l Option 2 s Develop a clock fan-out chip with a clock skew function for each output è Here, the ADC is somewhat (but not much) simpler but an additional ASIC is required l Option 1a, 1b appears attractive as it safely solves essentially all problems with a reduced number of ASICs EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

VFE to FE Data transmission l Available bandwidth (FEC12) s E.g. 3 lpGBTs * ( Mbit eLinks Mbit eLinks) l Implement one (640 Mbit) or two ( Mbit) eLinks in every ADC / QIE for data streaming s Macro exists for *** 130nm è Define CMS ECAL requirements early on in order to get incorporated s A few idle characters required in order to word-align at reception in the off detector electronics è E.g. upon BC0 reception; note that the arrival time of the BC0 needs to be skewed together with the clock è Imagine e.g. an all zeros – all ones – all zeros transition as ADC response to the BC0 EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Versatile link + l Plan to develop a ~uSD card sized combined receiver and 3 * transmitter s Would suit us well s Would take significantly less space than two short SFPs as of the Versatile Link l Studies ongoing to use Vcsel arrays s 4* Tx or 4* Rx; not necessarily attractive to CMS ECAL EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

LVRB replacement l A radiation and magnetic field tolerant ACDC power module has been developed which meets, a priori, our requirements s Investigate noise levels with an initial demonstrator s Determine grounding and shielding strategy s Develop LVRB respecting the mechanical requirements EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Bulk power system l Essentially all LHC upgrade projects are planning to use DCDC POL converters in or close to the front end system l The DCDC converters developed to date allow up to 12V input, essentially non-regulated. l A common project, similar to the legacy, is starting up in order to investigate the feasibility of operating COTS bulk power supplies in the experimental cavern l I suggest we participate to that common project s For info, I have an offer for a COTS bulk supply that could allow powering a full ECAL SM with redundant power for about 5000 USD EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Bias (HV) power system l Essentially, the requirements have not changed, thus the HV power system can be maintained. s The key word is “maintained” s The complete system will very likely need to be renewed purely due to age. This has already started. EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

ADC l No or little discussion about the future ADC l ADC development within the community not always successful l Previous experience very good s Buy a core and integrate in ASIC with rad tol design rules l Investigating possibility to go down the same route this time around s i.e. make a common development l A specification early on is instrumental s Number of channels (gains), Resolution, special functions (e.g gain switching), etc. EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Current EB R&D plan for TP l Develop the upgraded front end power system demonstrator s Develop a carrier for e.g. the DCDC module described last Tuesday afternoon by Federico Faccio s Evaluate with legacy front end system s Look out for issues with Noise and Thermal management l Develop a front end card Demonstrator s Streaming data to the back end s Look out for issues with Thermal management l Study existing CMS back end cards and define requirements for the future ECAL back end system s E.g. cards developed for the CMS level 1 trigger phase 1 upgrade EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

Phase 2 ECAL Barrel FE electronics system EB phase 2 electronics upgrade kick-off M. Hansen, CERN. HSSer lpGBT ADC - I2c interface? - Clock phase adjust? -Synch signal time skew? -Test pulse skew? -Baseline DACs? Pre-Amplifier -Test pulse injection? -I2c interface? -Baseline DACs? VFE card FE card 10.24Gbps 2.56Gbps Controls Data stream + control handshake Data stream LV regulator board, with rad tol DCDC

The end. EB phase 2 electronics upgrade kick-off M. Hansen, CERN.

GBT eLinks l Three lines: Clock, Data in, Data out l Clock can be 40 MHz s Receive and transmit clock generated in internal pll s Receive clock can be as low as 80 MHz s Transmit clock is the eLink speed l Sampling of Data in line is automatically optimized but no word alignment; serial stream essentially sent to logic. EB phase 2 electronics upgrade kick-off M. Hansen, CERN.