Test Architecture Design and Optimization for Three- Dimensional SoCs Li Jiang, Lin Huang and Qiang Xu CUhk Reliable Computing Laboratry Department of Computer Science & Engineering The Chinese University of Hong Kong

Outline Introduction Motivation Proposed approach Experiments Conclusion

Introduction 3D technique Vertically stack dices TSV as interconnect Benefit of 3D IC Interconnect Performance, Power, Area Memory bandwidth Heterogeneous technology 3D SoCs

Bonding Methods in 3D Technology W2W bonding Bond->Cut->Package Test Low yield D2D/D2W bonding Utilize pre-bond test Test->Cut->Bond Only stack KGD

Motivation Traditional SoC test architecture optimization 3D SoC test architecture optimization

Problem Definition Given Set of cores, Test Parameters, Position Available TAM width Determine Number of TAM Core assignment Width of each TAM Objective Minimize the total test cost C Total = C Test-Time * α+ C Wire-Length *(1- α) C Test-Time = C 3DChip + Σ C Layer C Wire-Length depends on routing model

Routing Model TAM for post-bond test TAM segments for pre-bond test Additional test pad TSV linking segments together Routing cost model Wire length: Manhattan distance between core centers Neglect length of TSV Wire length * TAM width

Approach Simulated annealing Appropriate for this scale Solution representation Core assignment & TAM width Move Move core Change TAM width Large solution space Proposed approach Outer SA-based core assignment Inner TAM width distribution heuristic

Approach Overflow Outer SA-based core assignment Redundancy in representation Rules to eliminate redundancy 1-to-1 corresponding between representation and solution Prove of completeness

Approach Greedy inner TAM width allocation procedure

Experiment Setup Baseline algorithms TR-1: Apply existing optimization algorithm to the 3D SoC layer by layer Adjust the TAM width among layers iteratively Optimize the pre-bond test architecture TR-2: Apply existing optimization algorithm to the whole 3D chip Optimize the post-bond test architecture Benchmark: ITC02 SoC benchmark Map to 3D SoC Previous wrapper optimization algorithm Testbus as TAM

Experimental Results

Conclusion Focus on D2D/D2W Pre-bond test and post-bond test Proposed efficient and effective approach can optimize the 3D Test Architecture To reduce the solution space, we split Simulated Annealing based approach into two part Experimental results show the efficiency of proposed approach

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