Tezzaron Semiconductor 04/27/2015 New Trends in Advanced 3D Vertical Interconnect Technology 1

Tezzaron Semiconductor 04/27/2015 Major Industry Thrusts Production –Improving yields –Reducing cycle time Heterogeneous integration Photonics is the new area of interest –Photonics are physically large and cd’s are large 65nm to 130nm technology range used –But … it needs 28nm technology for the drivers and receivers –Wire load can be >90% of the power unless 2.5/3D integrated 2

Tezzaron Semiconductor 04/27/2015 The Commercial Drivers Benefits of building devices joined through 3-D integration: –Form factor Reduced volume and weight –Performance improvements Improved integration density Improved transmission speed –Faster signal processing / increased sampling rate Reduced signal noise Reduced power consumption –Reduced manufacturing costs Single-wafer dicing Less packaging Simpler PCB (if needed at all)

Tezzaron Semiconductor 04/27/2015 Additive Integration Start with FEOL CMOS wafer Build novel structures BEOL Memories, CMOS, Photonics, III-V, Novel Materials, Microfluidics, MEMS, etc.

Tezzaron Semiconductor 04/27/2015 Sensor Creation through 3D Integration Si Substrate RDL 1.Wafer thinning 2.Through-Si-Via (TSV) etch 3.TSV fill and DBI Bond layer 4.Bond to CMOS wafer Can be repeated to create multi-wafer stacks

Tezzaron Semiconductor 04/27/2015 Toolbox of 3-D Integration Processes Tungsten TSV Liftoff Lithography Silicide/W/Al interconnects CU BEOL Copper Direct Bond Copper TSV

Tezzaron Semiconductor 04/27/2015 Toolbox Processes Bonding –SiO –Cu-Cu –Wafer-to-wafer –Die-to-wafer TSVs –Tungsten 2-0.6um –Copper 80-5um –Filled –Conformal ALD Split-Fab –≥28nm BEoL –≥65nm –High K caps ff/squm –Precision resistors Trenching –TSV-less 3D Materials –Platinum –Gold –Beryllium –Hafnium –Tantalum –Carbon, NT, graphene 7

Tezzaron Semiconductor 04/27/2015 Improving Technologies Bonding alignment improvement –250nm, (3σ) on 300mm wafers TSV backside insertion alignment –100nm (3σ) 150C max processing temperature Die singulation particle reduction –Down stream plasma etching 8

Tezzaron Semiconductor 04/27/2015 Interposers, Silicon or Organic? 9

Tezzaron Semiconductor 04/27/2015 Active 3D Sensor Programs at Tezzaron IBM 90nm –3D ROIC –25 x 15x15mm Jazz 130nm –3D ROIC –20x20mm GF 130nm –3D ROIC –85 x 10x10mm HW 150nm –3D ROIC –77K –15x15mm 1.4um pitch CMOS 3 tier integrated sensor 10

Tezzaron Semiconductor 04/27/2015 Leveraging 3-D Capabilities Vertically Integrated Photon Imaging Chip Multiple 3-D stacks fully integrated –Digital –Analog –Sensors Most sensitive detector ever demonstrated

Tezzaron Semiconductor 04/27/  m no p spray  m  m  m  m Wafer numbers

Tezzaron Semiconductor 04/27/2015 Full wafer R. Lipton 13 TS-1 Ts-2 TS- 3 TS- 4 TS- 5 TS-6 HGC- 1 HGC- 2 PS AL-1 CL- 1 SL-1 SR- 1 SR- 2 AL-2 ST-1 ST-2 CS- 1 CS- 2 CS- 3 ss1 ss2 ss3 ss4 ss5 ss6 ss7 ss8 ss9 ss10 ss11 ss12 ss13 ss14 ss15 ss16 ss17 ss18 ss19 ss20 ss21 ss22 ss23 ss24 ss25 ss26 ss27 ss28 ss29 ss30 ss31

Tezzaron Semiconductor 04/27/ D with III-V/Si integration 3-D achieves direct interconnect of InP/GaN wafers and Si wafers  Schematic, Cross-sectional, and top view of 3D CMOS/InP/GaN and graphene integrations  Demonstration of fine-grained wafer scale integration using 5um pitch interconnect between an InP wafer and a bulk CMOS wafer using DBI bonding

Tezzaron Semiconductor 04/27/

Tezzaron Semiconductor 04/27/2015 New Memories DiRAM4 SyoPort-P DiRAM4 SyoPort-S HMC2HBM2 Density 64 Gb 32 Gb 8 GB 4 GB Latency9 ns Variable ~15-40ns Variable ~18-45ns Variable ~75-800ns 33 ns Min Ref64 bits 256 bits Interface0.7 V0.7 – 1.2 V1.2 VSerDes1.2 V tRC15 ns 50 ns48 ns BW 16 Tb/s1 Tb/s4Tb/s 1 Tb/s 2 TB/s128 GB/s500 GB/s 128 Gb/s Channels2564/1 8/16 Banks per /4

Tezzaron Semiconductor 04/27/2015 Next: NDP/ Processor in Memory 64 light weight cores –~32GOPS + 1Tb/s external request traffic + 3Tb/s route through traffic 4 port –~1Tb/s/port Built-in full crossbar 64Gb Packet based –Nodal addressing support Memory fabric is the machine fabric 17

Tezzaron Semiconductor 04/27/2015 ReRAM Standalone or BEOL add-on technology –3 rd party wafers can be augmented to have 10’s-100’s of megabytes of modifiable nonvolatile storage Zero standby power High speed 10ns R/W >10e12 endurance BiSTAR enabled for extended reliablity >10 year retention 18

Tezzaron Semiconductor 04/27/

Tezzaron Semiconductor 04/27/2015 What happens if you boil all the liquid? 20

Tezzaron Semiconductor 04/27/2015 Summary 2.5/3D market is in the early adoption cycle –Moving from novelty to mainstream Drivers are: –Heterogeneous integration –Reducing power –Increasing performance Markets are: –Logic – memory –Sensors Next up: –Photonics