Lec 15Systems Architecture1 Systems Architecture Lecture 15: A Simple Implementation of MIPS Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan Some or all figures from Computer Organization and Design: The Hardware/Software Approach, Third Edition, by David Patterson and John Hennessy, are copyrighted material (COPYRIGHT 2004 MORGAN KAUFMANN PUBLISHERS, INC. ALL RIGHTS RESERVED).

Lec 15Systems Architecture2 Introduction Objective: To understand how to implement the MIPS instruction set. Combine components (registers, memory, ALU) and add control Fetch-Execute cycle Topics –Sequential logic (elements with state) and timing (edge triggered) Memory Registers –Datapath components: Instruction memory, PC, Adder, Register File, ALU, Data Memory –Implement a subset of MIPS in a single cycle computer –Shortcomings of a single cycle computer

Lec 15Systems Architecture3 The Processor: Datapath & Control Implementation of MIPS Simplified to contain only: –memory-reference instructions: lw, sw –arithmetic-logical instructions: add, sub, and, or, slt –control flow instructions: beq, j Generic Implementation: –use the program counter (PC) to supply instruction address –get the instruction from memory –read registers –use the instruction to decide exactly what to do

11/13/2015Chapter 4 — The Processor4 Instruction Execution PC  instruction memory, fetch instruction Register numbers  register file, read registers Depending on instruction class –Use ALU to calculate Arithmetic result Memory address for load/store Branch target address –Access data memory for load/store –PC  target address or PC + 4

Lec 15Systems Architecture5 Abstract View Two types of functional units: –elements that operate on data values (combinational) –elements that contain state (sequential)

11/13/2015Chapter 4 — The Processor6 Multiplexers Can’t just join wires together Use multiplexers

11/13/2015Chapter 4 — The Processor7 Control

Lec 15Systems Architecture8 Timing Clocks used in synchronous logic – when should an element that contains state be updated? Edge-triggered timing cycle time rising edge falling edge

Lec 15Systems Architecture9 Edge Triggered Timing State updated at clock edge Read contents of some state elements, Send values through some combinational logic Write results to one or more state elements

11/13/2015Chapter 4 — The Processor10 Logic Design Basics §4.2 Logic Design Conventions Information encoded in binary –Low voltage = 0, High voltage = 1 –One wire per bit –Multi-bit data encoded on multi-wire buses Combinational element –Operate on data –Output is a function of input State (sequential) elements –Store information

13 November 2015Chapter 4 — The Processor11 Combinational Elements AND-gate –Y = A & B A B Y I0 I1 Y MuxMux S Multiplexer Y = S ? I1 : I0 A B Y + A B Y ALU F Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B)

11/13/2015Chapter 4 — The Processor12 Sequential Elements Register: stores data in a circuit –Uses a clock signal to determine when to update the stored value –Edge-triggered: update when Clk changes from 0 to 1 D Clk Q D Q

11/13/2015Chapter 4 — The Processor13 Sequential Elements Register with write control –Only updates on clock edge when write control input is 1 –Used when stored value is required later D Clk Q Write D Q Clk

11/13/2015Chapter 4 — The Processor14 Clocking Methodology Combinational logic transforms data during clock cycles –Between clock edges –Input from state elements, output to state element –Longest delay determines clock period

Lec 15Systems Architecture15 Components for Simple Implementation Functional Units needed for each instruction

11/13/2015Chapter 4 — The Processor16 Instruction Fetch 32-bit register Increment by 4 for next instruction

11/13/2015Chapter 4 — The Processor17 R-Format Instructions Read two register operands Perform arithmetic/logical operation Write register result

11/13/2015Chapter 4 — The Processor18 Load/Store Instructions Read register operands Calculate address using 16-bit offset –Use ALU, but sign-extend offset Load: Read memory and update register Store: Write register value to memory

11/13/2015Chapter 4 — The Processor19 Branch Instructions Read register operands Compare operands –Use ALU, subtract and check Zero output Calculate target address –Sign-extend displacement –Shift left 2 places (word displacement) –Add to PC + 4 Already calculated by instruction fetch

11/13/2015Chapter 4 — The Processor20 Branch Instructions Just re-routes wires Sign-bit wire replicated

11/13/2015Chapter 4 — The Processor21 Composing the Elements First-cut data path does an instruction in one clock cycle –Each datapath element can only do one function at a time –Hence, we need separate instruction and data memories Use multiplexers where alternate data sources are used for different instructions

11/13/2015Chapter 4 — The Processor22 R-Type/Load/Store Datapath

11/13/2015Chapter 4 — The Processor23 Full Datapath

Lec 15Systems Architecture25 Adding Control Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction op rs rt rdshamtfunct op rs rt 16 bit address op 26 bit address RIJRIJ

Lec 15Systems Architecture26 MIPS Instructions add $t0,$s1,$s2 lw $t0,256($t1) op rs rt rd shamt funct op rs rt offset

Lec 15Systems Architecture27 MIPS Instructions Continued beq $s1,$s2,25 => 100 j 1024 => 4096 [+PC+4[31-28]] op address op rs rt offset

Lec 15Systems Architecture28 Determining ALU Control Bits ALUOp determined by instruction Control Lines 000 and 001 or 010 add 110 sub 111 slt

Lec 15Systems Architecture29 Must describe hardware to compute 3-bit ALU control input –given instruction type 00 = lw, sw 01 = beq, 10 = arithmetic –function code for arithmetic Describe it using a truth table (can turn into gates): ALUOp computed from instruction type ALU Control

Lec 15Systems Architecture30 Datapath with Control

Lec 15Systems Architecture31 Control Line Settings 8 control lines (control read/write and multiplexors)

13 November 2015Chapter 4 — The Processor32 R-Type Instruction

13 November 2015Chapter 4 — The Processor33 Load Instruction

13 November 2015Chapter 4 — The Processor34 Branch-on-Equal Instruction

13 November 2015Chapter 4 — The Processor35 Implementing Jumps Jump uses word address Update PC with concatenation of –Top 4 bits of old PC –26-bit jump address –00 Need an extra control signal decoded from opcode 2address 31:2625:0 Jump

13 November 2015Chapter 4 — The Processor36 Datapath With Jumps Added

Lec 15Systems Architecture37 Shortcomings of a Single Cycle Implementation Limits reuse of hardware components –each functional unit can be used only once per cycle –e.g. instruction and data memory required Inefficient –clock cycle determined by longest possible path in the machine –E.G. Assume time for: Memory units = 200 ps ALU and adders = 100 ps Register file (read or write) = 50 ps Instruction class Instruction memory Register read ALU operation Data memoryRegister writeTotal R-type ps Load word ps Store word ps Branch ps Jump ps

Lec 15Systems Architecture38 Single Cycle Model is inefficient! Assume 25% loads, 10% stores, 45% ALU instructions, 15% branches, and 5% jumps CPU execution time = Instruction count x CPI x Clock cycle time Performance ratio = CPU Performance (Multicycle impl.) = CPU Performance (Single cycle impl.) CPU Exec. Time (Single cycle impl.) = CPU Exec. Time (Multicycle impl.) = 600 x 25% x 10% x 45% x 15% x 5% 600 ps = 1.34 faster ps