Datapath and Control: MultiCycle Implementation

Performance of Single Cycle Machines °Assume following operation times: Memory units : 200 ps ALU and adders : 100 ps Register File (read or write): 50 ps Mux, control unit, PC access, sign extension unit, wires : 0 ps Instr. ClassFunctional units used Total time R-type Instr. Fetch (200 ps) Reg access (50 ps) ALU (100 ps) Reg access (50 ps) 400ps Load word Instr. Fetch (200 ps) Reg access (50 ps) ALU (100 ps) Mem. Access (200 ps) Register access (50 ps) 600 ps Store Word Instr. Fetch (200 ps) Reg access (50 ps) ALU (100 ps) Mem. Access (200 ps) 550 ps Branch Instr. Fetch (200 ps) Reg access (50 ps) ALU (100 ps) 350 ps Jump Instr. Fetch (200 ps) 200 ps Clock cycle must cover longest instruction  cycle period = 600ps (inefficient!)

Clocking: single-cycle vs. multicycle Single-cycle Implementation add $t0,$t1,$t2 beq $t0,$t1,L waste clock

Multicycle Implementation °Instruction execution divided into steps °Each step will take one clock cycle (not each instruction) [CPI > 1]  shorter clock cycle: cycle time constrained by longest step, not longest instruction °simpler instructions take fewer cycles  higher overall performance

Clocking: single-cycle vs. multicycle add $t0,$t1,$t2 beq $t0,$t1,L Single-cycle Implementation Multicycle Implementation add $t0,$t1,$t2 beq $t0,$t1,L Multicycle Implementation: less waste=higher performance waste clock

How fast can we run the clock? °Depends on how much we want done per clock cycle Can do: several “inexpensive” datapath operations per clock -simple gates (AND, OR, …) -single datapath registers (PC) -sign extender, left shifter, multiplexor PLUS: exactly one “expensive” datapath operation per clock -ALU operation -Register File access (2 reads, or 1 write) -Memory access (read or write)

Multicycle Instruction Execution 1: fetch instruction, PC=PC+4 2: decode, fetch registers, branch target 3: execute/compute data address/branch 4: access memory/complete R-type 5: store memory content to register

Recall: Single Cycle Datapath and Control

Steps CycleR-format Load Word (lw) Store Word (sw) beq 1 Fetch instr, PC = PC+4 Fetch instr. PC = PC+4 Fetch instr, PC = PC+4 Fetch instr, PC = PC+4 2 Read registers, calculate branch target address Read registers, calc branch target address 3Do computation Calc data address Compare reg values, set PC 4 Write result to register Read data memory Write to data memory 5Write data to register

Multicycle Datapath (overview) Registers Read Reg1 ALUALU Read Reg2 Write Reg Data PCPC Address Instruction or Data Memory MIPS-lite Multicycle Version A B ALU- Out Instruction Register Data Memory Data Register Read data 1 Read data 2 One ALU (no extra adders) One Memory (no separate Imem, Dmem) New Temporary Registers

Multicycle Implementation °Datapath changes one memory: both instructions and data (because can access on separate steps) one ALU (eliminate extra adders) extra “invisible” registers to capture intermediate (per-step) datapath results

Multicycle Datapath: Add Multiplexors ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 zero 15:11 Note inputs to multiplexors

Multicycle Datapath: Add Multiplexors ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 zero 15:11 Note inputs to multiplexors

Datapath + Control Points ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA ALUSrcB MemtoReg ALU Control ALUOp (funct) 5:0 MuxMux PCSrc PCWrite PCWrite- Cond

Cycle 1 Datapath: IR=Mem[PC]; PC=PC+4 ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 4 (funct) 5:0 MuxMux IR=Mem[PC]; PC=PC+4 IorD=0 MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=0 ALUSrcB=01 MemtoReg=x ALUOp=00 2 PCSrc=0 PCWrite PCWrite- Cond

Cycle 2: A=Reg[IR25:21]; B=Reg[IR20:16]; ALUOut= PC + sgn-ext(IR15:0) << 2 ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control (funct) 5:0 MuxMux A=Reg[IR 25:21 ]; B=Reg[IR 20:16 ]; ALUOut= PC + sgn-ext(IR 15:0 ) << 2 IorD=x MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=0 ALUSrcB=11 MemtoReg=x ALUOp=00 2 PCSrc=x PCWrite PCWrite- Cond

Cycle 3: R-format: ALUOut = A op B ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 4 (funct) 5:0 MuxMux ALUOut=A op B IorD=x MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=1 ALUSrcB=00 MemtoReg=x ALUOp=10 2 PCSrc=x PCWrite PCWrite- Cond

Cycle 4 R-format: Reg[IR15:11] = ALUOut ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 4 (funct) 5:0 MuxMux Reg[IR 15:11 ] = ALUOut IorD=x MemRead MemWrite IRWrite RegDst=1 RegWrite ALUSrcA=x ALUSrcB=x MemtoReg=0 ALUOp=x 2 PCSrc=x PCWrite PCWrite- Cond

Cycle 3 beq: if (A==B) PC =ALUOut ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 ALU Control 2 4 (funct) 5:0 MuxMux if (A==B) PC =ALUOut IorD=x MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=1 ALUSrcB=00 MemtoReg=x ALUOp=01 2 PCSrc=01 PCWrite PCWrite- Cond

Cycle 3 lw/sw: ALUOut = A + sgn-ext(IR15:0) ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=x MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=1 ALUSrcB=10 MemtoReg=x ALU Control ALUOp= (funct) 5:0 MuxMux PCSrc=x PCWrite PCWrite- Cond ALUOut = A + sgn-ext(IR 15:0 )

Cycle 4 lw : MDR = Mem[ALUout] ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=1 MemRead MemWrite IRWrite RegDst=x RegWrite ALUSrcA=x ALUSrcB=x MemtoReg=x ALU Control ALUOp=x (funct) 5:0 MuxMux PCSrc=x PCWrite PCWrite- Cond MDR = Mem[ALUout]

Cycle 5 lw: Reg[IR15:11] = MDR ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=x MemRead MemWrite IRWrite RegDst=0 RegWrite ALUSrcA=x ALUSrcB=x MemtoReg=1 ALU Control ALUOp=x (funct) 5:0 MuxMux PCSrc=x PCWrite PCWrite- Cond Reg[IR 15:11 ] = MDR

Cycle 4 ( sw ): Mem[ALUOut] = B ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD=1 MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA ALUSrc MemtoReg ALU Control ALUOp (funct) 5:0 MuxMux PCSrc PCWrite PCWrite- Cond Mem[ALUOut] = B

Datapath + Control Points ALUALU Regs Read Reg1 Read data1 Read data2 Read Reg2 Write Reg Write Data Sgn Ext- end PCPC << 2 A B ALU- Out Address Read Data Mem Write Data MDRMDR MuxMux 25:21 20:16 15:0 0 1M2 u 3 x MuxMux MuxMux MuxMux IR 4 z 15:11 IorD MemRead MemWrite IRWrite RegDst RegWrite ALUSrcA ALUSrcB MemtoReg ALU Control ALUOp (funct) 5:0 MuxMux PCSrc PCWrite PCWrite- Cond

Complete datapath

Fig Summary of steps taken

All write control signals not asserted explicitly are deasserted All Multiplexer controls not specified explicitly are don’t care asserted if name only otherwise exact value 1 FSM for Main Control Unit 0

Main Control Unit