1 VeLo L1 Read Out Guido Haefeli VeLo Comprehensive Review 27/28 January 2003

2 VeLo Read Out System VeLo TTCrxDriver Repeater board Equaliser ADC TTC 40m Analog electrical links Read out board Event Sync L1 Pre Processor L1B DAQ IF FEM TTC Shielding wall TTCrx To L1TTo DAQ ECS 1m I2C VREG Crate balcony 15m CAT6 Measured for 60m Attenuation Crosstalk

3 VeLo ROB board functionality n Reads 64 channels or 2048 detector strips. n Individual clock delay and reference voltage for each channel. n Event synchronization and consistency check based on a FE-chip located on each board. n Individual strip pedestal correction. n L1 buffering during 64ms. n Advanced common mode and zero suppression for the L1 trigger. n Zero suppression for the DAQ. n CC-PC based ECS n TTCrx

4 VeLo digitizer board functional overview L1 Decision Sync Error detection TTCrx FE emulator TFC Link L1T Cluster Fragment Link L1 zero suppression, clusterization To L1T event building network L1 Buffer controller L1 Buffer DAQ Interface DAQ Cluster Fragment Link To DAQ Delay Vref JTAG Ctrl Interface I2C Parallel ctrl ECS Ethernet Error Flagged ADC Analog data ADC Throttle Clk

5 Common mode suppression algorithms n LCMS (Linear Common Mode Suppression) u Applied on 1 analog channel (32 detector channels ). 8 bit precision. The LCMS algorithm is now the baseline version for the CM suppression. It has shown very good performances. n Regions (RCMS) u These are the same algorithm as LCMS but the linear correction are applied to 8 or 16 detector channels only. Its performance is of course better for non linear CM noise suppression. n Finite Impulse Response (FIR) filter u Its performance for suppressing non linear noise is by its nature much better than the LCMS type. With a FIR filter algorithm fine tuning can be done in order to suppress non linear CM. Tested by mixing "noise" coming from test beam data and "signal" B  from Monte-Carlo (See LHCb VeLo )

6 Prototyping

7RB2 4 analog channelsTTCrx moduleALTERA FLEX FPGA for simple data processing VME interface for data acquisition and board control 2048 word sample buffer8-bit 40MHz

8 RB2 Summary RB2 has been tested in the lab and in testbeams for performance measurements (see LHCb note ). To improve from RB2: u Improve clock distribution on the board (hardware modification have been implemented on existing RB2s ). u Introduce a clock adjustment for each ADC channel to cope with the delay skew on the cable.

9 L1 Link FPGA L1 Link card FE Emulator DAQ Link FPGA Sync FPGA TTCrx 4 CH ADC Card L1 Pre Processor L1B and DAQI Connector ECS RB3 Readout board

10 RB3 tests

11 Beetle setup

12 Outlook to the final ROB (64 Channel Digitizer Board) n Common project for several sub- detectors in LHCb. n The board can also be used with optical receiver cards. n Specification is in preparation, release February 2003 n Pre-production September 2003 n Testing until April 2004 n Final board production July Channel ADC Sync CC-PC TTCrx Power Input 32 Channel ADC Input PP L1T DAQ Link RAMRAMRAMRAM