Universidade Federal de Santa Catarina Centro Tecnológico Computer Science & Electrical Engineering Lectures 33 to 36 Combinational Circuits in CMOS Digital Integrated Circuits INE 5442 / EEL 7312 Prof. José Luís Güntzel

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 2 INE 5442 / EEL 7312 Digital Integrated Circuits Complementary CMOS Pass-Transistor Logic Agenda

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 3 INE 5442 / EEL 7312 Digital Integrated Circuits Combinational vs. Sequential Logic Combinational Logic in0 in1... ink out0 out1... outj Combinational Logic in0 in1... inm out0 out1... outn State Output values depend only on the current input values (no feedback, no storage element). Output values depend on the current input values and on previous input values (feedback with/without storage element).

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 4 INE 5442 / EEL 7312 Digital Integrated Circuits Logic Families in CMOS Static CMOS Logic –Complementary CMOS –Ratioed Logic –Pass-Transistor Logic Dynamic CMOS Logic

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 5 INE 5442 / EEL 7312 Digital Integrated Circuits Metrics for Choosing a Gate Design/Family Area in silicon (related to number of transistors) Speed (propagation delay) Energy consumption/Power dissipation Robustness to noise Reliability Manufacturability “Depending on the application, the emphasis will be on different metrics.” (Rabaey; Chandrakasan; Nikolic, 2005)

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 6 INE 5442 / EEL 7312 Digital Integrated Circuits Static CMOS Logic Features: Robustness (low sensitivity to noise). Good performance. Low power consumption (no static consumption, except for leakage currents). Easy to design (good for novice designers…)

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 7 INE 5442 / EEL 7312 Digital Integrated Circuits Truth-table Logic-level symbol Transistor schematics in out inout inout Vdd Complementary Logic: the inverter

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 8 INE 5442 / EEL 7312 Digital Integrated Circuits Complementary Logic: mask layout for an inverter N N P well P-implant P P N Substrate P channel N channel Vdd N-implant Gnd

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 9 INE 5442 / EEL 7312 Digital Integrated Circuits Steady-state operation inout Transistors seemed as ideal electronic switches Capacitance represents the total charge at the gate´s output in=0out=1 C L = Vdd Vdd in=1 out=0 C L = 0 V Vdd (in=Vdd) Complementary Logic: the inverter

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 10 INE 5442 / EEL 7312 Digital Integrated Circuits Complementary Logic in1 in2 in3 Vdd GND out = f(in1, in2, in3) PMOS only makes f(in1, in2, in3) = 1 NMOS only makes f(in1, in2, in3) = 0 pull-up network pull-down network in1 in2 in3 Pull-up and pull-down networks are mutually exclusive transistor associations (dual) In steady state, there is always a path to either Vdd or GND! (In steady state, the output is always a low-impedance node.)

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 11 INE 5442 / EEL 7312 Digital Integrated Circuits Discharging the output capacitance… Charging the output capacitance… Static CMOS Logic output CLCL 0  Vdd Vdd S D output CLCL Vdd  |V Tp | S D output CLCL Vdd Vdd  0 D S output CLCL Vdd 0  Vdd - V Tn Vdd D S V GS

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 12 INE 5442 / EEL 7312 Digital Integrated Circuits NMOS Series/Parallel Associations A X B Y X=Y if A=1 AND B=1 control variables Problem: NMOS transistors pass a weak “1” (but a strong “0”) X=Y if A=1 OR B=1 A X B Y control variables

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 13 INE 5442 / EEL 7312 Digital Integrated Circuits PMOS Series/Parallel Associations X=Y if A=0 AND B=0 A X B Y X=Y if A=0 OR B=0 A X B Y Problem: PMOS transistors pass a weak “0” (but a strong “1”) control variables

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 14 INE 5442 / EEL 7312 Digital Integrated Circuits Complementary Logic in1 in2 in3 Vdd GND out = f(in1, in2, in3) PMOS only; makes f(in1, in2, in3) = 1 NMOS only; makes f(in1, in2, in3) = 0 pull-up network pull-down network in1 in2 in3 Only negative logic functions are implemented (e.g.: inverter, NAND, NOR, XNOR…) Design procedure: –use the “0” of the gate function to design the pull-down network –Apply De Morgan´s theorem to find the pull-up network. An n-input logic gate requires 2n transistors.

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 15 INE 5442 / EEL 7312 Digital Integrated Circuits ABS A S B A S B A B Vdd Complementary Logic: 2-input Nand Truth-table Logic-level symbol Transistor schematics

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 16 INE 5442 / EEL 7312 Digital Integrated Circuits A Out V DD GND B A S B A B Vdd Complementary Logic: 2-input Nand mask layout

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 17 INE 5442 / EEL 7312 Digital Integrated Circuits Steady state behavior: 4 possible input combinations A=0 S=1 B=0 A=0 B=0 C L =Vdd Vdd A=0 S=1 B=1 A=0 B=1 C L =Vdd Vdd A=1 S=0 B=1 A=1 B=1 C L =0 V Vdd A=1 S=1 B=0 A=1 B=0 C L =Vdd Vdd ABS Complementary Logic: 2-input Nand

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 18 INE 5442 / EEL 7312 Digital Integrated Circuits Delay characterization through electric-level simulation (e.g., Spice) Complementary Logic: 2-input Nand B A S tp LH(A) tp HL(A) tp LH(B) tp HL(B) A S B input tp LH (ps) tp HL (ps) A B Evaluates the individual contribution of each input (the others are kept at their non-controlling values)

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 19 INE 5442 / EEL 7312 Digital Integrated Circuits A Out V DD GND B A S B A B Vdd Complementary Logic: 2-input Nand

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 20 INE 5442 / EEL 7312 Digital Integrated Circuits ABS A S B A S B A B Vdd Truth-table Logic-level symbol Transistor schematics Complementary Logic: 2-input Nor

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 21 INE 5442 / EEL 7312 Digital Integrated Circuits S = A+B·C Example: A S B C Building Complementary CMOS Complex Gates 1.If the logic gate equation is not negated, imagine it as it were. At the end, an extra inverter will have to be added. (Alternatively, apply De Morgan´s theorem…) 2.Take the non-inverting equation of the logic gate to design the pull-down network

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 22 INE 5442 / EEL 7312 Digital Integrated Circuits S = A+B·C Example: A S B A B C C Vdd 3.Design the pull-up network by finding the dual of the pull-down network, already designed: 1.Each series NMOS association gives rise to a parallel PMOS association 2.Each parallel NMOS association gives rise to a series PMOS association Building Complementary CMOS Complex Gates

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 23 INE 5442 / EEL 7312 Digital Integrated Circuits Properties of Complementary CMOS Gates Full rail-to-rail swing; high noise margins (V OH =Vdd, V OL =GND) Logic levels not dependent upon the relative device sizes; ratioless Always a path to Vdd or Gnd in steady state; low output impedance Extremely high input resistance; nearly zero steady-state input current No direct path steady state between power and ground; no static power dissipation Propagation delay function of load capacitance and resistance of transistors Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 24 INE 5442 / EEL 7312 Digital Integrated Circuits RpRp A RpRp A RnRn CLCL B RpRp A RpRp A RnRn B RnRn CLCL C int NAND2INVNOR2 CLCL B RnRn A RpRp B RpRp A RnRn C int Switch Delay Models for Complementary Gates Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 25 INE 5442 / EEL 7312 Digital Integrated Circuits Delay is dependent on the pattern of inputs Low to high transition –both inputs go low delay is 0.69 R p /2 C L –one input goes low delay is 0.69 R p C L High to low transition –both inputs go high delay is R n C L Delay Depends on the Input Pattern Source: Rabaey; Chandrakasan; Nikolic, 2005 CLCL B RnRn A RpRp B RpRp A RnRn C int

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 26 INE 5442 / EEL 7312 Digital Integrated Circuits Delay Depends on the Input Pattern A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 100 fF Sized for tp LH =~ tp HL Source: Rabaey; Chandrakasan; Nikolic, 2005 EntradasAtraso (ps) A=B=0  169  A=1, B=0  150  A= 0  1, B=162  A=B=1  035  A=1, B=1  057  A= 1  0, B=176 

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 27 INE 5442 / EEL 7312 Digital Integrated Circuits Delay Depends on the Input Pattern A=B=1  0 A=1, B=1  0 A=1  0, B=1 time [ps] Voltage [V] NMOS = 0.5  m/0.25  m PMOS = 0.75  m/0.25  m C L = 100 fF Sized for tp LH =~ tp HL Source: Rabaey; Chandrakasan; Nikolic, 2005 B=1 S=0 A=1 B=1 C L =0 V Vdd Cint=0 V B=1 S=1 A=0 B=1 C L =Vdd Vdd Vdd-VTn

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 28 INE 5442 / EEL 7312 Digital Integrated Circuits The V T of the two NMOS transistors are calculate by: The “Body Effect” Source: Rabaey; Chandrakasan; Nikolic, 2005 V Tn2 = Vtn0 +  (( 2  f + V int ) 0.5 – (2  f ) 0.5 ) V Tn1 = V tn0 B S A A B Vdd M1 M2 int

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 29 INE 5442 / EEL 7312 Digital Integrated Circuits Transistor Sizing Distributed RC model (“Elmore Delay”) t pHL = 0,69  (R 1  C 1 + (R 1 +R 2 )  C (R 1 +R 2 +R 3 )  C 3 + (R 1 +R 2 +R 3 +R 4 )  C L ) If R 1 =R 2 =R 3 =R 4 then: t pHL = 0.69 R eqn (C 1 +2C 2 +3C 3 +4C L ) CLCL C R7R7 D R8R8 A R4R4 B R3R3 C3C3 A R5R5 B R6R6 C R2R2 D R1R1 C1C1 C2C2 Considering intra-cell capacitances

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 30 INE 5442 / EEL 7312 Digital Integrated Circuits Gates with more than 4 inputs should be avoided… t pL H t p (ps) fanin t pHL quadratic linear tptp Propagation Delay as a Function of Fan-In Source: Rabaey; Chandrakasan; Nikolic, 2005 Propagation delay of CMOS NAND gate

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 31 INE 5442 / EEL 7312 Digital Integrated Circuits t p NOR2 t p (psec) eff. fan-out All gates have the same drive current. t p NAND2 t p INV Slope is a function of “driving strength” Propagation Delay as a Function of Fan-Out Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 32 INE 5442 / EEL 7312 Digital Integrated Circuits Fan-in: quadratic due to increasing resistance and capacitance Fan-out: each additional fan-out gate adds two gate capacitances to C L t p = a 1 FI + a 2 FI 2 + a 3 FO Propagation Delay as a Function of Fan-Out Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 33 INE 5442 / EEL 7312 Digital Integrated Circuits Transistor sizing –Desde que a capacitância de saída domine Progressive sizing In N CLCL C3C3 C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 MN RC distribuído W M1 > W M2 > W M3 > … > W MN (o trans. mais próximo da saída tema a menor resistência de canal.) Pode reduzir o atraso da porta em até 20% (segundo Rabaey) Design Techniques for Static CMOS Gates Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 34 INE 5442 / EEL 7312 Digital Integrated Circuits Transistor ordering C2C2 C1C1 In 1 In 2 In 3 M1 M2 M3 CLCL C2C2 C1C1 In 3 In 2 In 1 M1 M2 M3 CLCL Critical path 1 0101 charged 1 O Atraso é determinado pelo tempo para descarregar C L, C 1 e C 101 charged Critical path charged O Atraso é determinado pelo tempo para descarregar C L Source: Rabaey; Chandrakasan; Nikolic, 2005 Design Techniques for Static CMOS Gates

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 35 INE 5442 / EEL 7312 Digital Integrated Circuits Explorando a Decomposição Lógica F = ABCDEFGH Lógica de 2 níveis em CMOS Elevando fanin (evitar) Faninlimitado a 2, fanout unitário Source: Rabaey; Chandrakasan; Nikolic, 2005 Design Techniques for Static CMOS Gates

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 36 INE 5442 / EEL 7312 Digital Integrated Circuits Isolamento de carga elevada usando buffer CLCL CLCL Design Techniques for Static CMOS Gates Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 37 INE 5442 / EEL 7312 Digital Integrated Circuits Cell Design Standard Cells –General purpose logic –Can be synthesized –Same height, varying width Datapath Cells –For regular, structured designs (arithmetic) –Includes some wiring in the cell –Fixed height and width Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 38 INE 5442 / EEL 7312 Digital Integrated Circuits Standard Cell Layout Methodology – 1980s signals Routing channel V DD GND Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 39 INE 5442 / EEL 7312 Digital Integrated Circuits Standard Cell Layout Methodology – 1990s M2 No Routing channels V DD GND M3 V DD GND Mirrored Cell Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 40 INE 5442 / EEL 7312 Digital Integrated Circuits Standard Cells Cell boundary N Well Cell height 12 metal tracks Metal track is approx Pitch = repetitive distance between objects Cell height is “12 pitch” 2 Rails ~10 In Out V DD GND Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 41 INE 5442 / EEL 7312 Digital Integrated Circuits Standard Cells In Out V DD GND InOut V DD GND With silicided diffusion With minimal diffusion routing Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 42 INE 5442 / EEL 7312 Digital Integrated Circuits Standard Cells A Out V DD GND B 2-input NAND gate Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 43 INE 5442 / EEL 7312 Digital Integrated Circuits Stick Diagrams Contains no dimensions Represents relative positions of transistors In Out V DD GND Inverter A Out V DD GND B NAND2 Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 44 INE 5442 / EEL 7312 Digital Integrated Circuits Stick Diagrams C AB X = C (A + B) B A C i j j V DD X X i GND AB C PUN PDN A B C Logic Graph Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 45 INE 5442 / EEL 7312 Digital Integrated Circuits Two Versions of C (A + B) X CABABC X V DD GND V DD GND Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 46 INE 5442 / EEL 7312 Digital Integrated Circuits Consistent Euler Path j V DD X X i GND AB C ABC Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 47 INE 5442 / EEL 7312 Digital Integrated Circuits OAI22 Logic Graph C AB X = (A+B)(C+D) B A D V DD X X GND AB C PUN PDN C D D A B C D Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 48 INE 5442 / EEL 7312 Digital Integrated Circuits Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 49 INE 5442 / EEL 7312 Digital Integrated Circuits Pass Transistor Logic Exemplo 1: uma função arbitrária (com 4 vars. de controle) saída A’ B’ A B E1 E2 ABsaída 00E1’ E2’ Saída = A  B  E2’+A’  E1’+B’  E1’ buffer N transistores Sem consumo estático

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 50 INE 5442 / EEL 7312 Digital Integrated Circuits Vx não consegue atingir Vdd, mas Vdd -VTn(Vx) (efeito de corpo) Tensão na entrada do inversor não é suficiente para desligar o transistor PMOS Mensagem: não cascatear transistores de passagem, conectando-os a gates de outras estruturas similares. ~ O Comportamento do Transistor de Passagem Tempo [ns] x Out In Tensão [V] Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 51 INE 5442 / EEL 7312 Digital Integrated Circuits NMOS-only Switch A =2.5 V B C =2.5 V C L A =2.5 V C =2.5 V B M 2 M 1 M n Threshold voltage loss causes static power consumption V B does not pull up to 2.5V, but 2.5V - V TN NMOS has higher threshold than PMOS (body effect) Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 52 INE 5442 / EEL 7312 Digital Integrated Circuits NMOS Only Logic: Level Restoring Transistor M 2 M 1 M n M r Out A B V DD V Level Restorer X Advantage: Full Swing Restorer adds capacitance, takes away pull down current at X Ratio problem Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 53 INE 5442 / EEL 7312 Digital Integrated Circuits Restorer Sizing W/L r =1.0/0.25 W/L r =1.25/0.25 W/L r =1.50/0.25 W/L r =1.75/0.25 V o l t a g e [V] Time [ps] 3.0 Upper limit on restorer size Pass-transistor pull-down can have several transistors in stack Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 54 INE 5442 / EEL 7312 Digital Integrated Circuits Solution 2: Single Transistor Pass Gate with V T =0 Out V DD V 2.5V V DD 0V 2.5V 0V WATCH OUT FOR LEAKAGE CURRENTS Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 55 INE 5442 / EEL 7312 Digital Integrated Circuits Complementary Pass Transistor Logic Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 56 INE 5442 / EEL 7312 Digital Integrated Circuits Solution 3: Transmission Gate A B C C A B C C B C L C = 0 V A =2.5 V C =2.5 V Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 57 INE 5442 / EEL 7312 Digital Integrated Circuits Resistance of Transmission Gate Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 58 INE 5442 / EEL 7312 Digital Integrated Circuits Pass-Transistor Based Multiplexer GND V DD In 1 In 2 SS S S Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 59 INE 5442 / EEL 7312 Digital Integrated Circuits Transmission Gate XOR A B F B A B B M1 M2 M3/M4 Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 60 INE 5442 / EEL 7312 Digital Integrated Circuits Delay in Transmission Gate Networks C R eq R CC R C In m (c) Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 61 INE 5442 / EEL 7312 Digital Integrated Circuits Delay Optimization Source: Rabaey; Chandrakasan; Nikolic, 2005

Lectures 33 to 36 Prof. Güntzel Combinational Circuits in CMOS 62 INE 5442 / EEL 7312 Digital Integrated Circuits Transmission Gate Full Adder Similar delays for sum and carry Source: Rabaey; Chandrakasan; Nikolic, 2005