Coincidence Detector on SOPC Coincidence Detector on SOPC Final Presentation Presenting: Roee Bar & Gabi Klein Instructor:Ina Rivkin Technion – Israel Institute of Technology Department of Electrical Engineering High Speed Digital Systems Lab

Final Presentation Agenda Project Goals Project Goals Implementation Method Implementation Method Algorithm Algorithm Technical Details Technical Details Implementation Limitations Implementation Limitations DCM Capabilities DCM Capabilities System Description System Description Results Results Achievements Achievements Future Developments Future Developments

Final Presentation Goals Additional Goals: Create a Signal Generator, which will be used to test the detector. Create a Signal Generator, which will be used to test the detector. Thoroughly understand the features and capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro. Thoroughly understand the features and capabilities of the Digital Clock Manager (DCM) on the Virtex II Pro. Main Goal: Detect two simultaneous events

Final Presentation Implementation Method Implementation Method The detector and the generator will be implemented on the Virtex II Pro platform, using the Xilinx XUPV2P Development Board. The detector and the generator will be implemented on the Virtex II Pro platform, using the Xilinx XUPV2P Development Board. The detector unit will detect coincidence of two events in a given timeframe. The detector unit will detect coincidence of two events in a given timeframe.

Final Presentation Reminder In reality, the probability of the two events occurring exactly at the same time is practically zero. Therefore, we have to define a timeframe T. In reality, the probability of the two events occurring exactly at the same time is practically zero. Therefore, we have to define a timeframe T. Two events occurring in this timeframe, are called coincident events. Two events occurring in this timeframe, are called coincident events. T

Final Presentation Algorithm Let’s examine a coincidence between two signals: Let’s examine a coincidence between two signals: A B A XOR B W Declare coincidence if W<T. Declare coincidence if W<T. Target: Find out if W<T. Target: Find out if W<T.

Final Presentation Algorithm Let’s examine the following circuit, where the clock cycle is T: Let’s examine the following circuit, where the clock cycle is T: 2: W>T/2 1: 0<W<T 0: W<T/2 We assume that if coincidence occurred W T. We assume that if coincidence occurred W T. If F<2 we declare coincidence. If F<2 we declare coincidence. SRFF A XOR B CLOCK’ CLOCK S Clk Q S Q SRFF F Counts the number of ‘1’ A AND B ‘2’ 0 1

Final Presentation Algorithm We can improve resolution and detect W<2T/N. We can improve resolution and detect W<2T/N. Let’s take N phase shifted clocks where the k-th clock is shifted by kT/N Let’s take N phase shifted clocks where the k-th clock is shifted by kT/N Then, we’ll connect all the SRFF outputs to a counter. Then, we’ll connect all the SRFF outputs to a counter.

Final Presentation Algorithm S Clk1 Q A XOR B S Clk2 Q S Clk3 Q S In1 In2 In3 InN Counts the Number of ‘1’ inputs With the result of F, we can determine the signal pulse width range in resolution of 2T/N. S ClkN Q A AND B ‘N’ F F=k<N → (k-1)T/N<W<(k+1)T/N F=N → W>(N-1)T/N

Final Presentation Technical Details System clock frequency: 100MHz. System clock frequency: 100MHz. We will use DCM to double the clock frequency to 200Mhz. We will use DCM to double the clock frequency to 200Mhz. DCMs used for implementation – 3 DCMs used for implementation – 3 Each DCM has 4 outputs, 4 evenly shifted clocks, which gives us total of 12 shifted clocks. Each DCM has 4 outputs, 4 evenly shifted clocks, which gives us total of 12 shifted clocks. This gives ability to determine signal pulse width in resolution of 2T/N=832pSec. This gives ability to determine signal pulse width in resolution of 2T/N=832pSec.

Final Presentation Implementation Limitations In practice the coincidence detects correctly when W T+d. When T-d T+d. When T-d<W<T+d the detector output is not defined. In our case: d=417ps, T=5ns. In our implementation we do not report the pulse length but only report coincidence when W T+d. In our implementation we do not report the pulse length but only report coincidence when W T+d. After each coincidence the signals should be stable for 2 clock cycles (~20nSec). After each coincidence the signals should be stable for 2 clock cycles (~20nSec). Due to flip-flops metastability some signals might not be detected correctly. Due to flip-flops metastability some signals might not be detected correctly.

Final Presentation DCM Capabilities The main capability of a DCM is clock de- skewing. Phase Shifting: Each DCM is capable of driving the input clock in 4 different clock phases, separated by 90° each. Frequency Synthesis: Input frequency multiplied by two, divided by an integer between 2 and 16, multiplied by M, divided by D. By using these methods, we are capable to create almost any frequency between 3MHz and 420 MHz.

Detector Final Presentation The Detector unit consists of 3 Mini Detection blocks and a Controller The Detector unit consists of 3 Mini Detection blocks and a Controller Controller Mini Detection Blocks with DCM

Detector Final Presentation Mini Detection Block DCM SRFF Each Mini Detection block consists of 4 SRFF which handle 4 timeframes. Each Mini Detection block consists of 4 SRFF which handle 4 timeframes.

Signal Generator Final Presentation The Signal Generator produces tests signals for the Detector. The Signal Generator produces tests signals for the Detector. Each test consists of two time shifted signals. Each test consists of two time shifted signals.

Signal Generator Final Presentation DCM Controller DCM Latch

Results Final Presentation When A XOR B pulse is detected by all detectors – there is no coincidence (Detected output is low). When A XOR B pulse is detected by all detectors – there is no coincidence (Detected output is low).

Results Final Presentation When A XOR B pulse is not detected by all detectors – there is a coincidence (Detected output is high). When A XOR B pulse is not detected by all detectors – there is a coincidence (Detected output is high).

Final Presentation Achievements Studied ISE, ChipScope, HDL Designer, Precision and ModelSim. DCM configuration and usage. Developed a method to detect coincidence using digital components only. Implemented a Signal Generator to test our Coincidence Detector.

Final Presentation Future Development When reporting a coincidence, also report the estimated pulse width. Improving the Coincidence Detector precision by using higher clock frequency or using more DCM units. Overcome the system metastability issue.

Final Presentation