TRIO-CINEMA 1 UCB, 2/08/2010 Cinema Stein Interface FPGA (CSI) [Part II] Karthik Lakshmanan CINEMA - EE Team Space Sciences Laboratory University of California, Berkeley

TRIO-CINEMA 2 UCB, 2/08/2010 Cinema Stein Interface FPGA - Agenda AGENDA  Overview  Block Diagrams  Requirements  CSI Components  Development Plan

TRIO-CINEMA 3 UCB, 2/08/2010 Overview (1/2) Overall Context CSI is an Actel FPGA that resides in the STEIN electronics.

TRIO-CINEMA 4 UCB, 2/08/2010 Overview (2/2) Functional Description of CSI

TRIO-CINEMA 5 UCB, 2/08/2010 CSI Block Diagram

TRIO-CINEMA 6 UCB, 2/08/2010 Requirements IDTitleRequirement STE-05STEIN Count RateCount up to 30,000 events/sec/detector (TBR) SFE-03ADC4 channels 16 bit >100KHz ADC SFE-04Threshold4 channels programmable LLD DACs, 8+ bits SHV-02SweepProgrammable up to 16 (TBR) steps/second with < 4 ms (TBR) timing jitter with 1% (TBR) of full scale resolution. Outputs are independently programmable (TBR) CDI Interface16 bits/ADC-Conv, 80KHz events = 1.28Mbps + 16 bits descriptive tag = 32 bits per event record Interface bit rate = 8.4MHz, Data rate = 4Mbps (includes CDI Protocol and Message Tag Overhead, “fixed message size” mode)

TRIO-CINEMA 7 UCB, 2/08/2010 CSI Components (1) Cinema STEIN Interface FPGA Modules FIXED DAC CONTROL Handles all the LLD Threshold DAC values. 6 DACS onboard Inputs: SYNCH REGS_CMDPARMS Registers:Fixed DAC Values(4) Outputs: FDDAC: (CK, LD, CLR, DAT) Load DACs with updated voltage value.

TRIO-CINEMA 8 UCB, 2/08/2010 CSI Components (2) Cinema STEIN Interface FPGA Modules SWEEP DAC CONTROL Controls 2 Sweep DACs which increment the detector voltage periodically. It also periodically (once/second) loads two fixed DACs (BIAS and TestPulser). IDLE SYNCH & ACCUMINT ENABLE SWEEP RESET SYNCH RD LUT LD DAC DONE ACCUMINT DONE 128 steps/second => 32 steps/sweep and 4 sweeps/second. Lookup table based => reconfigurable Inputs ACCUMINT:. At every rising edge the SWEEP DAC voltage is updated from the LUT. CYCCOUNTS: CMDPARMS SRAMDATIN: Next voltage value read from LUT. Outputs SWDAC: (CK, LD, CLR, DAT) Load DACs with updated voltage value.

TRIO-CINEMA 9 UCB, 2/08/2010 CSI Components (3) LUT MEMORY  It stores the voltage pattern that the Sweep DAC has to follow.  512 bytes of memory (out of 4.25kB available)  Loaded by REGS module  Read by SWEEP DAC module Inputs: SRAMDATIN(15:0) Input to memory. This is used when the table is loaded. REGS_ADR Address Input from REGS module SDAC_ADRAddress Input from SDAC module REGS_WR: Write to LUTM SDAC_RD:Read from LUTM ENBSWEEP: State of Sweep Subsystem (LUT Write-protected when Sweep is Active) Outputs: SRAMDATOUT(15:0): Voltage data read from table

TRIO-CINEMA 10 UCB, 2/08/2010 CSI Components (4) REGS (Command Interface)  Handles interfacing with off-board systems via CDI (Command Data Interface)  Interface bit rate = 8.4MHz, Data rate = 4Mbps (includes CDI Protocol)  Stores all command parameters. Commands become active at the 1 second tick after they were set. Inputs CMDCLK: Command Clock. Possibly the same as SCLK. The target frequency is 8.34MHz. CMDDAT: Command Data Outputs REGS_CMDPARAMS: Command Parameters. These include all Register data. Parity and Framing Errors are detected, and commands discarded if an error is present. No feedback is given regarding error-detection or command rejection. * A detailed description of this interface can be found in pages of Reference 3 (MAVEN PFDPU to Instrument ICD).

TRIO-CINEMA 11 UCB, 2/08/2010 CSI Components (5) Serial Command Timing CDI (Command Data Interface) *  Falling Clock Edge to prevent conflict between CMD and CLK signals  System synchronises using Start/Stop bits  The parity is odd and includes the 24 command bits but not the start bit  Command Format is as shown below: * A more detailed description of this interface can be found in pages of Reference 3 (MAVEN PFDPU to Instrument ICD).

TRIO-CINEMA 12 UCB, 2/08/2010 Development Plans Development  Specification : Revision A just released  FPGA coding language : VHDL  Coding of modules: To begin shortly  Testing: All modules will be unit tested in VHDL