1 CAPS Compilers Activities IRISA Campus Universitaire de Beaulieu Rennes

2 CAPS TEAM Architecture –André Seznec (Director of Research, CAPS group leader) –Pierre Michaud (Researcher) –Jacques Lenfant (Professor) –Thierry Lafage (PhD) –Jonathan Perret (PhD) –Romain Dolbeau (PhD) Compiler –F. Bodin (Professor) –Antoine Monsifrot (PhD) –Ronan Amicel (PhD) –Gilles Pokam (PhD) –Laurent Bertaux (PhD) –Laurent Morin (PhD) –Karine Heydemann (PhD)

3 Background Architecture –high performance (co-)processors –superscalar microprocessors –memory hierarchy –branch prediction mechanism,... Compiler –high performance computing –parallel computing –optimizations for VLIW –preprocessor infrastructures –code transformations

4 Compiler Activities Code optimizations for embedded applications –infrastructures –optimizing compiler strategies Global constraints –code sizes –low power (starting) Interactive tools –code tuning –case based reasoning –assembly code optimizations

5 Overview Interface Front-end Target Description(s) Code Generation Back-end Optimizer Instruction set Simulator tool 2 tool 1 tool 3 tool 4 feedback

6 Fortran Code Optimization Provides tools for code tuning –user oriented –case based reasoning –static code analysis and pattern matching –profiling Infrastructure used –Foresys: Fortran interactive front-end (from Simulog) –TSF: Scripting language for program transformation (developed by CAPS) Bibliography: “FITS - A Light-Weight Integrated Programming Environment”, B. Chapman, F. Bodin, L. Hill, J. Merlin, G. Viland, F. Wollenweber, Euro-Par'99

7 Assembly Code Optimization Provide methods and tools for analyzing code quality and for fine grain tuning –VLIW architectures –navigation in the assembly code –access to profiling and compiler data –link with the source code Infrastructure used –Salto

8 High Performance Instruction Set Simulation Provide new generation techniques for instruction set simulation –high performance, simulation of large code, debugging –flexible –retargetable, experiment new instruction sets Infrastructure –Salto C Source TriMedia Assembly code tmcc TriMedia Binary generator tmsim tmas gcc/ld C++ Source compile simulation Architecture description

9 Scheduling Infrastructure SALTO2 –provide new infrastructure better suited for code optimization –more abstract interface –more integration with code generation Architecture Description D ® M Architecture Model Intermediate representation Opt 1Opt 2Opt n P ® RI Text Input D ® Ass (Emit) Optimized Program interface to IR Interfaces External Infrastructure User interface G.U.I. Intermediate Code

10 Preprocessor Multimedia Instruction Provide tools to help rewriting code source for exploiting multimedia instructions A S T CCMIR SWARgen Unparser IR Graph rewriting SWARcc Pattern matching COSY Rules C Code Declaration The SWAR SYSTEM

11 Iterative Compilation Dealing with global constraints Better control of tradeoffs Bibliography: H-263 “Handling Global Constraints in Compiler Strategy”, Erven Rohou, François Bodin, Christine Eisenbeis and André Seznec, to appear in International Journal of Parallel Programming