Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 1 ECE 406 – Design of Complex Digital Systems Lecture 7: Design Example, Modeling Flip-Flops Spring 2009 W. Rhett Davis NC State University with significant material from Paul Franzon, Bill Allen, & Xun Liu

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 2 Announcements l HW#3 Due Thursday l Exam #1 in 9 Days l HW#4 Due in 16 Days

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 3 Summary of Last Lecture l Does the order of procedural assignments matter? What about continuous assignments? l What does the event-list of an always block mean? l To model combinational logic procedurally, what variables must be in the event list? l Should variables assigned in a procedural block be declared as wire, reg, or either? l How do you prevent an unintentional latch?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 4 Today’s Lecture l Combinational Design Example l Flip-Flops, Blocking vs. Non-Blocking Assignments

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 5 Design Example l Design a module named “ALU”. l It has three 3-bit inputs A, B, and C and a 1-bit input E. l It has a 3-bit output R and a 1-bit output O. l When E is 1, » R is the bit-wise XOR of A and B, and » O is 1. l When E is 0, » R is the sum of B and C (both are assumed to be signed integers), and » O is the non-overflow indicator, which is 0 when signed overflow happens.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 6 A Word About Overflow l Unsigned Overflow occurs when Carry-Out is 1 l Signed Overflow occurs when » the sum of positive numbers is negative OR » the sum of negative numbers is positive …or, equivalently… » the MSBs of the operands are equal AND » the MSB and Carry-Out of the result differ

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 7 Design Example l Draw a schematic to represent the hardware

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 8 Design Example l Write the Verilog module using Data-Flow (continuous assignments) ONLY.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 9 Design Example l Write a procedural Verilog description (with

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 10 Design Example l What’s wrong with the following code?

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 11 Today’s Lecture l Combinational Design Example l Flip-Flops, Blocking vs. Non-Blocking Assignments

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 12 D Flip-Flop Timing Diagram D clock Q D Q Don’t know (Don’t care) “x” Glitches at input do not appear at output. F/F only samples ‘D’ at positive clock edge.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 13 D Flip-Flop Verilog Description D clock Q module flipflop (D, clock, Q); input D, clock; output Q; reg Q; clock) Q = D; endmodule posedge & negedge are keywords Could also be written as Q <= D; (what’s the difference?)

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 14 Blocking vs. Non Blocking l = is referred to as a blocking assignment, because execution of subsequent code is blocked until the assignment is made. l <= is referred to as non- blocking assignment. Essentially, all non-blocking right-hand-sides are evaluated but no assignments are made until the end of the procedural block. l Example: What’s the difference between the two code fragments to the right? T&M 1.3.3, Sutherland guide 10.2 clk) begin A = Y; B = A; end clk) begin A <= Y; B <= A; end

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 15 Inferring Hardware from Assignments l When given an clock) behavior and asked to draw a schematic, I follow these steps: » For every left-hand side of an assignment, draw a flip-flop whose output is connected to that signal » For non-blocking assignments (<=), set the input of each flip-flop to be the right-hand side of the last assignment for each variable » For blocking assignments (=), work back from the end to figure out the inputs to the flip-flops l When writing your own behavior, it is suggested that you use non-blocking assignments (<=), so that you don’t have to work back from the end.

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 16 Blocking vs. Non Blocking What hardware would be synthesized for this example? A = Y; B = A; A <= Y; B <= A;

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 17 Example reg A, B, C, D; clock) begin C = A; B = C; C = D; end

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 18 Example reg A, B, C, D; clock) begin C <= A; B <= C; C <= D; end

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 19 Example reg A, B, C, D; clock) begin if (A) D <= B; else D <= C; C <= D; end

Spring 2009W. Rhett DavisNC State UniversityECE 406Slide 20 Summary l How do you model a flip-flop? l What is the difference between blocking and non-blocking assignments? l How do you infer flip-flops for an clock) procedure with blocking or non-blocking assignments? l Is it better to use blocking or non-blocking assignments in an clock) procedure? Why?