Synchronous Counters Synchronous digital counters have a common clock which results in all the flip-flops being triggered simultaneously. Consequently, there are no cumulative delays that result because the clock signal must ripple through the stages as in the asynchronous counters. Synchronous counters can be designed to count up and down in numerical order. In addition, they may be used to produce count sequences of non- consecutive numbers. The count sequence produced by synchronous counters is not dependent on the trigger characteristics of the flip-flops that comprise the count stages. The count sequence is achieved by applying the required logic function into the flip-flops.

Synchronous Counter Analysis Verify that the counter is indeed synchronous (i.e. identify the common clock feature). Determine the number of stages by counting the number of flip- flops or outputs. Determine the type of flip-flops and the input function for each stage. For reference, recall the characteristic table which indicates the present state (Qt), the present inputs and the next state (Qt+1) for each flip flop. Construct a characteristic table for the complete counter circuit. Analyze the counter using the characteristic table to determine the complete counter sequence. This analysis concludes when the count sequence begins to repeat. Determine the modulus of the counter. Construct a state transition diagram to describe the counter operation. Graph the output waveforms produced by the counter.

A two-bit synchronous counter

J-K Flip-Flop Characteristic Table Present Inputs J K Present Next stateQt stateQt

Counter Characteristic Table

State transition diagram

Waveform Diagram for counter

Synchronous counter design To successfully design synchronous counters we may employ the following six basic steps: Create the state transition diagram. Create a present state-next state table (often referred to as the next state table). Expand the table to form the transition table for each flip-flop in the circuit. The transition table shows the flip-flop inputs required to make the counter go from present state to the desired next state. This is also referred to as the excitation table. Determine the logic functions of the J and K inputs as a function of the present states. Analyze the counter to verify the design. Construct and test the counter.

state transition diagram Let us employ these Techniques to design a MOD-8 counter to count in the following sequence: 0, 1, 2, 3, 4, 5, 6, 7.

Creating present state-next state table