A.Abhari CPS2131 Chapter 3: Gate-Level Minimization Topics in this Chapter: The Map Method Two-Variable Map Three- Variable Map Four/Five variable Map.

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Digital Logic Design Gate-Level Minimization

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Presentation transcript:

A.Abhari CPS2131 Chapter 3: Gate-Level Minimization Topics in this Chapter: The Map Method Two-Variable Map Three- Variable Map Four/Five variable Map Don’t –Care Conditions Product of Sums Simplification Implementing NAND and NOR circuits

A.Abhari CPS2132 The Map Method Truth table of f n is unique but f n can be in many different algebraic forms Simplification by using boolean algebra is often difficult because we don’t know how to proceed Map method or Karnaugh map (K_Map) is simple and straightforward method that produces minimum number of terms.

A.Abhari CPS2133 Two-Variable Map A f n variable have 2 n minterms (cells)

A.Abhari CPS2134

5 Three- Variable Map Adjacent cells represent minterms that differs by only one variable. Therefore, adjacent cells are identical except for one variable that appears complemented in one cell and uncomplemented in the adjacent cell. Example : F(x,y,z) = ∑ (2,3,4,5)

A.Abhari CPS2136 Another example : F(x,y,z) = ∑(3,4,6,7)

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10 Four variable Map

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A.Abhari CPS21323 Multilevel NAND circuits To convert multilevel AND-OR to all NAND: 1.Convert all ANDs with AND-invert 2.Convert all ORs with invert-OR 3.Check the bubbles in diagrams if any of them is not compensated by another small circle along the same line insert an inverter (it is one input NAND gate) or complement the input literal

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A.Abhari CPS21328 Implementing NOR circuits To convert multilevel AND-OR to all NOR: 1.Convert all ORs with OR-invert 2.Convert all ANDs with invert-AND 3.Check the bubbles in diagrams if any of them is not compensated by another small circle along the same line insert an inverter (one input NOR gate) or complement the input literal

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