Rome 4 Sep 04

Status of the Readout Electronics for the HMPID ALICE Jose C. DA SILVA ALICE

Rome 4 Sep 04 Introduction –RCB controller and DDL (SIU-DDU- PRORC) –Column Controller updates (Pedestals Readback, Trigger Inhibit, etc) –Busy Signal, (NIM Logic)

Rome 4 Sep 04 HMPID overview VME to Local Bus Interface Segment Controller fbD[31..0] LOC_ADD[11..0] LOC_CS LOC_R/Wn fbD[27..0] LOC_CS LOC_R/Wn LOC_ADD[3..0] Column Controller (1 to 8) DILO 5 Boards (ADC and DILOGIC) FE Boards (gassiplex) RCB BOARDSEGMENT

Rome 4 Sep 04 HMPID overview DDL SIU LINK HMPID DDL Controller Segment Controller fbD[31..0] SIU Control LOC_ADD[11..0] LOC_CS LOC_R/Wn TTC_RX TTC Bus L2 BUSY fbD[27..0] LOC_CS LOC_R/Wn LOC_ADD[3..0] Column Controller (1 to 8) DILO 5 Boards (ADC and DILOGIC) FE Boards (gassiplex) RCB BOARDSEGMENT

Rome 4 Sep 04 Readout and Control Board Embedded Controller that interfaces the DAQ link and the Segment Controllers. –>Modify all the interface method with the Segments and Columns Monitors the Segment and Link Status, stores the L1A informations, decodes the L2A via the TTC-Rx Broadcast bus and builds the event for the data selected at each L2A. L0, L1 and L2 NIM inputs (while no TTC system) Busy signal out (NIM logic, LVDS). The RCB Interface houses a TTC_rx and a SUI Link board, and logic level converters (NIM-TTL-NIM). –>TTC emulation while no TTC system

Rome 4 Sep 04 RCB Controller Main components of the RCB controller embedded on the ALTERA: Controller, basically a set of 2 synchronous state machines –one SM running at 40MHz for SIU interface –one SM running at 10MHz for Segment Interface TTC_Rx emulator (Event Number and Bx Number) –LHC structured counters Data FIFO, Controlled by both SM. HEADER builder Busy signal.

Rome 4 Sep 04 HMPID RCB HMPID RCB

Rome 4 Sep 04 Segment Controller -This controller interfaces with the RCB controller via a specific “local interface”, fully synchronous. -Allows a perfect modularity and repeatability of the design of the segment PCB’s. -Controls the bus access for the selected Column on each Segment. -Global signals fanout (Reset, Clock, Busy)

Rome 4 Sep 04 Segment Controller

Rome 4 Sep 04 Full Segment

Rome 4 Sep 04 Column Controller Self clock generator, Column setup functions (read, write and bypass selection) Gassiplex and Dilogic setup (track and hold, dilo and gassiplex phased clocks,), read and write of the Dilogics Data trough bi-directional FIFO’s, and interface with the Segment Controller. Programmable features: –Number of Clocks (16, 32, 48, 64) –Clock Frequency (10, 8, 5, 1.25 MHz) –Dilogic Channel Bypass

Rome 4 Sep 04 Column Controller

Rome 4 Sep 04 DDL Link (hardware and software) Full Equipped Segment Board –8 columns and 16 MCM Cards Full Control and Readout of all modules Test Beam 2003

Rome 4 Sep 04 Beam Tests (2003)