Parallel beam execution in FAIR: control system concepts and requiements for FESA J.Fitzek FESA Workshop, 27. Nov. 2012, GSI.

Slides:



Advertisements
Similar presentations
Improving Transaction-Time DBMS Performance and Functionality David Lomet Microsoft Research Feifei Li Florida State University.
Advertisements

CAL (CAN Application Layer) and CANopen J. Novák Czech Technical University in Prague Faculty of Electrical Engineering Department of Measurement.
Information System Engineering
Demands and Requirements for the New Control System for GSI Future Accelerators An Overview U. Krause, S. Richter, P. Schütt.
Copyright © 2013 Fluxicon Process Mining Tutorial.
CPSC 668Set 14: Simulations1 CPSC 668 Distributed Algorithms and Systems Spring 2008 Prof. Jennifer Welch.
Operating System Concepts with Java – 7 th Edition, Nov 15, 2006 Silberschatz, Galvin and Gagne ©2007 Processes and Their Scheduling.
1 Project Management Office Lunch & Learn Use Case.
Silberschatz, Galvin and Gagne  Operating System Concepts Chapter 5: Threads Overview Multithreading Models Threading Issues Pthreads Solaris.
1 Memory Management Virtual Memory Chapter 4. 2 The virtual memory concept In a multiprogramming environment, an entire process does not have to take.
CHP - 9 File Structures. INTRODUCTION In some of the previous chapters, we have discussed representations of and operations on data structures. These.
22 March 2012Dietrich Beck - BEL General Machine Timing FAIR Just a few slides….
Silberschatz, Galvin and Gagne  2002 Modified for CSCI 346, Royden, Operating System Concepts Operating Systems Lecture 24 Paging.
Your Logo 1 TREATMENT OF TIME IN A FLIGHT SIMULATOR In a real-time simulator, the most important resource to manage is time itself. A flight simulator.
Silberschatz, Galvin and Gagne ©2011Operating System Concepts Essentials – 8 th Edition Chapter 4: Threads.
Replication Mechanisms for a Distributed Time Series Storage and Retrieval Service Mugurel Ionut Andreica Politehnica University of Bucharest Iosif Charles.
Formal Model for Simulations Instructor: DR. Lê Anh Ngọc Presented by – Group 6: 1. Nguyễn Sơn Hùng 2. Lê Văn Hùng 3. Nguyễn Xuân Hậu 4. Nguyễn Xuân Tùng.
MapReduce: Simplified Data Processing on Large Clusters Jeffrey Dean and Sanjay Ghemawat.
Submission doc.: IEEE /1250r0 Oct Shusaku Shimada Yokogawa Co. Slide 1 TSF Timer Freq. Management and Measurement Procedure (TFM 2 P) Date:
Data and Computer Communications
1 Chapter 11 Extending Networks (Repeaters, Bridges, Switches)
WWWWhat timing services UUUUsage summary HHHHow to access the timing services ›I›I›I›Interface ›N›N›N›Non-functional requirements EEEExamples.
Hardware process When the computer is powered up, it begins to execute fetch-execute cycle for the program that is stored in memory at the boot strap entry.
Towards real-time camera based logos detection Mathieu Delalandre Laboratory of Computer Science, RFAI group, Tours city, France Osaka Prefecture Partnership.
FAIR Accelerator Controls Strategy
Operating Systems David Goldschmidt, Ph.D. Computer Science The College of Saint Rose CIS 432.
Jürgen Florenkowski GSI, Darmstadt Agenda Annual Report Meeting EU construction ( CNI ) contract "DIRAC-PHASE-1" for the FAIR project September 26, 2006.
CIS 112 Exam Review. Exam Content 100 questions valued at 1 point each 100 questions valued at 1 point each 100 points total 100 points total 10 each.
Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition, Lecture 7: CPU Scheduling Chapter 5.
CSE 461 University of Washington1 Where we are in the Course Finishing off the Link Layer! – Builds on the physical layer to transfer frames over connected.
Session 1 Introduction  What is RADE  Technology  Palette  Tools  Template  Combined Example  How to get RADE  Questions? RADE Applications EN-ICE-MTA.
Multiplexing in FESA. Alexander Schwinn 2 Overview Part I- The concept Part II- Before execution Part III- Setting a new Voltage to the Hardware Part.
FGC Upgrades in the SPS V. Kain, S. Cettour Cave, S. Page, J.C. Bau, OP/SPS April
Mining Document Collections to Facilitate Accurate Approximate Entity Matching Presented By Harshda Vabale.
Multithreaded Programing. Outline Overview of threads Threads Multithreaded Models  Many-to-One  One-to-One  Many-to-Many Thread Libraries  Pthread.
David Adams ATLAS DIAL: Distributed Interactive Analysis of Large datasets David Adams BNL August 5, 2002 BNL OMEGA talk.
Silberschatz, Galvin and Gagne ©2009 Operating System Concepts – 8 th Edition, Chapter 4: Threads.
International Accelerator Facility for Beams of Ions and Antiprotons at Darmstadt Construction of FAIR Phase-1 December 2005 J. Eschke, GSI Construction.
1 Pintos Virtual Memory Management Project (CS3204 Spring 2006 VT) Yi Ma.
Johnson Carmichael Kay Kummerfeld Hexel1 Context Evidence and Location Authority the disciplined management of sensor data into context models.
Pintos project 3: Virtual Memory Management
CERN Timing Overview CERN timing overview and our future plans with White Rabbit Jean-Claude BAU – CERN – 22 March
Lectures 8 & 9 Virtual Memory - Paging & Segmentation System Design.
Beam time structures 1 At any particular instance of time there will be only one kind of beam in the MI. It will be either protons or anti-protons. The.
CE Operating Systems Lecture 8 Process Scheduling continued and an introduction to process synchronisation.
Operating System Concepts
B2B Transfer System for FAIR (Conceptual Design [1]) Presenter: Jiaoni Bai Professor: Oliver Kester Supervisor: David Ondreka, Dietrich Beck.
Embedded Real-Time Systems Processing interrupts Lecturer Department University.
Industrial Control Engineering Session 1 Introduction  What is RADE  Technology  Palette  Tools  Template  Combined Example  How to get RADE 
General Architecture of Retrieval Systems 1Adrienn Skrop.
LSA Core overview 6 / 11 / 2007 Wojciech Śliwiński (AB-CO-AP) on behalf of LSA team.
ESS Timing System Plans Timo Korhonen Chief Engineer, Integrated Control System Division Nov.27, 2014.
Batch to Manufacturing Markup Language B2MML - V0400
2018/4/ /4/18 Project: IEEE P Working Group for Wireless Personal Area Networks (WPANs) Submission Title: Overview of Date Submitted:
FAIR Machine Cycles David Ondreka
Fundamentals of WEB Programming
Process Management Process Concept Why only the global variables?
CHP - 9 File Structures.
FCC Cryo-magnet Logistics
Timing Review FESA Requirements with respect to the current Timing implementation FESA Team FE section TimingReview FESA Requirements.
Managing Diffraction Beam
Chapter 2 Database Environment.
Chapter 5: CPU Scheduling
Ladies and Gentlemen, Let me give you a short outlook to the operating of the new facility at this point. My colleague has just shown you, how we operate.
Inter Process Communication (IPC)
Operating System Concepts
Timing System GSI R. Bär / U. Krause 15. Feb. 2008
Semester Review Brian Kocoloski
Operating System , Fall 2000 EA101 W 9:00-10:00 F 9:00-11:00
Chapter 13: I/O Systems.
Presentation transcript:

Parallel beam execution in FAIR: control system concepts and requiements for FESA J.Fitzek FESA Workshop, 27. Nov. 2012, GSI

FESA Workshop, Nov /13 Parallel beam execution in FAIR Agenda Operation of the FAIR facility Timing information within the Control System Requirements for FESA

FESA Workshop, Nov /13 Parallel beam execution in FAIR © Petra Schütt, GSI, 2012 FAIR facility

FESA Workshop, Nov /13 Parallel beam execution in FAIR Operation of the FAIR facility © David Ondreka, MAC Presentation, Oct up to 5 parallel beams optimize the duty-cycle support alternatives and dump scenarios focus on planning of „beams“ typically one main experiment per pattern, that defines the time frame, other experiments fill the gap no fixed pattern length, length vary with setting changes (e.g. energy) during daily operations, patterns are being activated / (re-)organized

FESA Workshop, Nov /13 Parallel beam execution in FAIR Terminology Pattern Beam Production Chain Supercycle

FESA Workshop, Nov /13 Parallel beam execution in FAIR Example for two active patterns Pattern 1: Protons and RIB, executed indefinitely Pattern 2: Plasma Physics, executed once every two hours when experiment requests the beam SIS18 SIS100 PP Unilac SIS18 SIS100 CR p-Linac Unilac Pre-PatternMain-PatternPost-Pattern Pre-PatternMain-PatternPost-Pattern

FESA Workshop, Nov /13 Parallel beam execution in FAIR further grouping? Contents of beam production chains InjRampeExtBeam-out SIS18 Beam-OutTfrBeam-outTfrBeam-out T1S1..T1S4 InjRampeExtBeam-out InjRampeEBeam-out SIS100 InjRampeExtraktion BPC 1 BPC 2

FESA Workshop, Nov /13 Parallel beam execution in FAIR Agenda Operation of the FAIR facility Timing information within the Control System Requirements for FESA

FESA Workshop, Nov /13 Parallel beam execution in FAIR FAIR Control System stack

FESA Workshop, Nov /13 Parallel beam execution in FAIR Planning of synchronized executions t ime sync, RT-control Data supply: schedules of IDs, alternatives Data supply: set values (with IDs) Settings Management (LSA)

FESA Workshop, Nov /13 Parallel beam execution in FAIR Timing System from an outside perspective The timing system: one central timing master, sends out events for the full facility (filtering on the timing receiver side) „executes“ BeamProcesses assumption: BPs are the smallest pieces that are always executed completely always sends out the full event, that contains: all necessary IDs a timestamp to make the execution unique event number to describe actions in the accelerator

FESA Workshop, Nov /13 Parallel beam execution in FAIR Agenda Operation of the FAIR facility Timing information within the Control System Requirements for FESA

FESA Workshop, Nov /13 Parallel beam execution in FAIR Requirements for FESA In general, FESA must be able to handle the indexing needed for the execution of patterns and chains. Requirements that arise are: FESA must allow the indexing of set values with the corresponding IDs implementation of the multiplexing context accordingly => similar concept needed for the upper layers too (JAPC, LSA) mapping of IDs to memory location? FESA must be able to put the full „event stamp“ to actual values if available, the full event stamp must be provided to the user allow for partial compare if user requests for all actual values of one BPC execution?