1 Instruction memory is used to store a program Processor gets one instruction at a time It stores it locally (like) I0, I1 registers PC points to next.

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Presentation transcript:

1 Instruction memory is used to store a program Processor gets one instruction at a time It stores it locally (like) I0, I1 registers PC points to next location –It is automatically incremented Control directs execution Another memory stores data Execution goes as follows LD/STADD/SUB/OR/XOR/ANDI0 <-- IMEM[PC], PC+ I1 <-- IMEM[PC], PC+Rz <-- (Rx) OP (Ry) Addr <-- (I1) Rx <-- DMEM[Addr] for LD, or DMEM [Addr] <-- Rx for ST Stored Program

2 PC points to next instruction that is to be executed by a machine However, user may want to change control flow They use a branch instruction and condition code For example if one wants to check if register R1 is greater than R2, we may subtract R2 from R1 and check the sign bit Sign bit one means result is negative and R1 is smaller than R2 SUB R0, R1, R2 BNEG neg pos: …… ……. neg: ……. …….. The conditions to check: –GT, LT, EQ, NE, GE, LE Conditional Branch Instruction

3 Consider a program segment to decide final grade If (grade < 50) then GRADE is fail (0) else if (grade < 60) then GRADE is D (1) else if (grade < 70) then GRADE is C (2) else if (grade < 80) then GRADE is B (3) else GRADE is A (4) we need to compare grade (say in register R1) with fixed values say in R2 (=50), R3(=60), R4(=70), R5(=80), and decide what to do How will we write the program? SUB R0, R1, R2 /* Sub R2 from R1 and store result into R0 */ BPOS g50 /* Branch if result is a positive value */ LD R3, ZERO /* Load value from location called zero */ BR Done /* we are done */ g50: SUB R0, R1, R3 /* Store R1-R3 into R0 */ BPOS g60 /* Branch if > 60 */ ….. Another Example: Deciding Grade

4 If the branch condition is met, then we want to change PC value with new value, else we just increment PC Branch address is part of instruction We need to copy new address in PC What change we need to make in data path? Accounting for Branch Condition Inst Mem PC WIAD IIAD IAddr INST Mem Unit WM EM Data Addr RM WDAD ALUALU OpCode Reg File WA WR RA2RA1 Input EI Output WOUT EALU M- Reg EMR SHIFTSHIFT SC Cond Code